JAJSII9 データシート

JAJSII9E april 2020 – june 2023 DRA821U , DRA821U-Q1

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メカニカル・データ（パッケージ｜ピン）

ALM|433

サーマルパッド・メカニカル・データ

発注情報

7.9.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset related signals.

Table 7-6 MCU_PORz Timing Requirements see Figure 7-10

NO.			MIN	TYP	UNIT
RST1	t_{h(MCUD_SUPPLIES_VALID - MCU_PORz)}	Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies valid (using external crystal)	N + 1200⁽²⁾	9500000	ns
RST2	t_{h(MCUD_SUPPLIES_VALID - MCU_PORz)}	Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies⁽¹⁾ valid and external clock stable (using external LVCMOS oscillator)	1200		ns
RST3	t_{w(MCU_PORzL)}	Pulse Width minimum, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO)	1200		ns

(1) For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.

(2) N = oscillator start-up time

Figure 7-10 MCU_PORz Timing Requirements

Table 7-7 PORz Timing Requirements see Figure 7-11

NO.			MIN	MAX	UNIT
RST4	t_{h(MAIND_SUPPLIES_VALID - PORz)}	Hold time, PORz active (low) at Power-up after all MAIN DOMAIN supplies1 valid	1200		ns
RST5	t_w(PORzL)	Pulse Width minimum, PORz low after Power-up	1200		ns

For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.

Figure 7-11 PORz Timing Requirements

Table 7-8 MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-12

NO.	PARAMETER		MODE	MIN	UNIT
RST10	t_{d(MCU_PORzL-MCU_RESETSTATzL)}	Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low)		0	ns
RST11	t_{d(MCU_PORzH-MCU_RESETSTATzH)}	Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high)	POST bypass	12000*S⁽¹⁾	ns
RST12	t_{d(MCU_PORzL-RESETSTATzL)}	Delay time, MCU_PORz active (low) to RESETSTATz active (low)		0	ns
RST13	t_{d(MCU_PORzH-RESETSTATzH)}	Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high)		14500*S⁽¹⁾	ns
RST16	t_{w(MCU_RESETSTATzL)}	Pulse Width Minimum MCU_RESETSTATz low		3900*S⁽¹⁾	ns
RST17	t_{w(RESETSTATzL)}	Pulse Width Minimum RESETSTATz low		2650*S⁽¹⁾	ns

(1) S = MCU_OSC0_XI/XO clock period.

Figure 7-12 MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics

Table 7-9 PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics see Figure 7-13

NO.	PARAMETER		MODE	MIN	UNIT
RST20	t_{d(PORzL-RESETSTATzL)}	Delay time, PORz active (low) to RESETSTATz active (low)		T⁽¹⁾
RST20	t_{d(PORzL-RESETSTATzL)}	Delay time, PORz active (low) to RESETSTATz active (low)	CTRLMMR_WKUP_POR_RST _CTRL[0].POR_RST_ISO_ DONE_Z = 0	0	ns
RST21	t_{d(PORzH-RESETSTATzH)}	Delay time, PORz active (high) to RESETSTATz active (high)		14500*S⁽²⁾	ns

(1) T = Reset Isolation Time (Software Dependent).

(2) S = MCU_OSC0_XI/XO clock period.

Figure 7-13 PORz initiates; RESETSTATz Switching Characteristics

Table 7-10 MCU_RESETz Timing Requirements see Figure 7-14

NO.			MIN	MAX	UNIT
RST22	t_{w(MCU_RESETzL)}⁽¹⁾	Pulse Width minimum, MCU_RESETz active (low)	1200		ns

(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.

Table 7-11 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-14

NO.	PARAMETER		MIN	UNIT
RST23	t_{d(MCU_RESETzL-MCU_RESETSTATzL)}	Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low)	800	ns
RST24	t_{d(MCU_RESETzH-MCU_RESETSTATzH)}	Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high)	3900*S⁽¹⁾	ns
RST25	t_{d(MCU_RESETzL-RESETSTATzL)}	Delay time, MCU_RESETz active (low) to RESETSTATz active (low)	800	ns
RST26	t_{d(MCU_RESETzH-RESETSTATzH)}	Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high)	3900*S⁽¹⁾	ns

(1) S = MCU_OSC0_XI/XO clock period.

Figure 7-14 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics

Table 7-12 RESET_REQz Timing Requirements see Figure 7-15

NO.			MIN	MAX	UNIT
RST27	t_{w(RESET_REQzL)}⁽¹⁾	Pulse Width minimum, RESET_REQz active (low)	1200		ns

(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.

Table 7-13 RESET_REQz initiates; RESETSTATz Switching Characteristics see Figure 7-15

NO.	PARAMETER		MODE	MIN	UNIT
RST28	t_{d(RESET_REQzL-RESETSTATzL)}	Delay time, RESET_REQz active (low) to RESETSTATz active (low)	software control of SOC_WARMRST_ISO_DONE_Z	T⁽¹⁾
RST28	t_{d(RESET_REQzL-RESETSTATzL)}		CTRLMMR_WKUP_MAIN_WARM _RST_CTRL[0].SOC_ WARMRST_ISO_DONE_Z = 0	740	ns
RST29	t_{d(RESET_REQzH-RESETSTATzH)}	Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high)		2650*S⁽²⁾	ns

(1) T = Reset Isolation Time (Software Dependent).

(2) S = MCU_OSC0_XI/XO clock period.

Figure 7-15 RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics

Table 7-14 EMUx Timing Requirements see Figure 7-16

NO.			MIN	MAX	UNIT
RST30	t_{su(EMUx-MCU_PORz)}	Setup time, EMU[1:0] before MCU_PORz inactive (high)	3*S⁽¹⁾		ns
RST31	t_{h(MCU_PORz - EMUx)}	Hold time, EMU[1:0] after MCU_PORz inactive (high)	10		ns

(1) S = MCU_OSC0_XI/XO clock period.

Figure 7-16 EMUx Timing Requirements

Table 7-15 MCU_BOOTMODE Timing Requirements see Figure 7-17

NO.			MIN	MAX	UNIT
RST32	t_{su(MCU_BOOTMODE-MCU_PORz)}	Setup time, MCU_BOOTMODE[09:00] before MCU_PORz high	3*S⁽¹⁾		ns
RST33	t_{h(MCU_PORz - MCU_BOOTMODE)}	Hold time, MCU_BOOTMODE[09:00] after MCU_ PORz high	0		ns

(1) S = MCU_OSC0_XI/XO clock period.

Figure 7-17 MCU_BOOTMODE Timing Requirements

Table 7-16 BOOTMODE Timing Requirements see Figure 7-18

NO.			MIN	MAX	UNIT
RST34	t_{su(BOOTMODE-PORz)}	Setup time, BOOTMODE[7:0] before PORz high	3*S⁽¹⁾		ns
RST35	t_{h(PORz - BOOTMODE)}	Hold time, BOOTMODE[7:0] after PORz high	0		ns

(1) S = MCU_OSC0_XI/XO clock period.

Figure 7-18 BOOTMODE Timing Requirements