JAJSII9 データシート

JAJSII9E april 2020 – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

ALM|433

サーマルパッド・メカニカル・データ

発注情報

7.9.5.12 I3C

For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Table 7-42, Table 7-43, Figure 7-75, Table 7-44, and Figure 7-76 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 7-42 I3C Open Drain Timing Conditions

PARAMETER		MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate	0.2276	5	V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance		50	pF

Table 7-43 I3C Open Drain Timing Parameters

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	t_{LOW_OD}	Low Period of SCL Clock	Controller	200		ns
D1	t_{DIG_OD_L}	Low Period of SCL Clock	Controller	t_{LOW_OD MIN} + t_{FDA_OD MIN}		ns
D2	t_HIGH	High Period of SCL Clock	Controller		41	ns
D2	t_{DIG_H}	High Period of SCL Clock	Controller		t_HIGH + t_CF	ns
D3	t_{fDA_OD}	Fall Time of SDA Signal	Controller, Target	t_CF	12	ns
D4	t_{SU_OD}	SDA Data Setup Time During Open Drain Mode	Controller, Target	3		ns
D5	t_CAS	Clock After START (S) Condition	Controller, ENTAS0	38.4	1000	ns
			Controller, ENTAS1	38.4	100000	ns
			Controller, ENTAS2	38.4	2000000	ns
			Controller, ENTAS3	38.4	50000000	ns
D6	t_CBP	Clock Before STOP (P) Condition	Controller	t_{CAS MIN} / 2		ns
D7	t_MMOVERLAP	Current Controller to Secondary Controller Overlap time during handoff	Controller	t_{DIG_OD_Lmin}		ns
D8	t_AVAL	Bus Available Condition	Controller	1000		ns
D9	t_IDLE	Bus Idle Condition	Controller	1000000		ns
D10	t_MMLOCK	Time Internal Where New Controller Not Driving SDA Low	Controller	t_AVALmin		ns

This is approximately equal to t_LOWmin + t_{DS_ODmin} + t_{rDA_ODtyp} + t_{SU_Odmin}.
The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already above V_IH.
Based on t_SPIKE, rise and fall times, and interconnect.
This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (for example: a short Bus).
On a Legacy Bus where I2C Devices need to see Start, the t_CAS Min value is further constrained.
Targets that do not support the optional ENTASx CCCs shall use the t_CAS Max value shown for ENTAS3.
On a Mixed Bus with Fm Legacy I2C Devices, t_AVAL is 300ns shorter than the Fm Bus Free Condition time (t_BUF).

Figure 7-75 I3C Open Drain Timing

Table 7-44 I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
D1	f_SCL	SCL Clock Period	Controller	80	100000	ns
D2	t_LOW	SCL Clock Low Period	Controller	24		ns
D2	t_{DIG_L}	SCL Clock Low Period	Controller	32		ns
D3	t_{HIGH_MIXED}	SCL Clock High Period of Mixed Bus (Mixed Bus Topology Not Supported)	Controller	24		ns
D3	t_{DIG_H_MIXED}		Controller	32	45	ns
D4	t_HIGH	SCL Clock High Period	Controller	24		ns
D4	t_{DIG_H}	SCL Clock High Period	Controller	32		ns
D5	t_SCO	Clock in to Data Out for Target	Target	12		ns
D6	t_CR	SCL Clock Rise Time	Controller	150 × 1 / f_SCL	60	ns
D7	t_CF	SCL Clock Fall Time	Controller	150 × 1 / f_SCL	60	ns
D8	t_{HD_PP}	SDA Signal Data Hold in Push Pull Mode	Controller	t_CR + 3 and t_CF + 3		ns
D8	t_{HD_PP}	SDA Signal Data Hold in Push Pull Mode	Target	0		ns
D9	t_{SU_PP}	SDA Signal Data Setup In Push-Pull Mode	Controller, Target	3		ns
D10	t_CASr	Clock After Repeated START (Sr)	Controller	t_{CAS MIN}		ns
D11	t_CBSr	Clock Before Repeated START (Sr)	Controller	t_{CAS MIN} / 2		ns

FSCL = 1 / (t_{DIG_L} + t_{DIG_H})
t_{DIG_L} and t_{DIG_H} are the clock Low and High periods as seen at the receiver end of the I3C Bus using V_IL and V_IH.
When communicating with an I3C Device on a mixed Bus, the t_{DIG_H_MIXED} period must be constrained to make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling.
As both edges are used, the hold time needs to be satisfied for the respective edges; t_CF + 3 for falling edge clocks, and t_CR + 3 for rising edge clocks.
Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz

Figure 7-76 I3C Push-Pull Timing (SDR and HDR-DDR Modes)