JAJSII9E april 2020 – june 2023 DRA821U , DRA821U-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Specifically, the DDR subsystem supports LPDDR4 devices compliant to the JEDEC JESD209-4B standard. DDRSS0 is accessed via MSMC, and not directly through the system interconnect.
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.