JAJSII9 データシート

JAJSII9E april 2020 – june 2023 DRA821U , DRA821U-Q1

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ALM|433

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発注情報

7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	MIN	MAX	UNIT
NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	133 MHz		UNIT
FA0	t_w(be[x]nV)	Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time	Read		N^⁽¹²⁾	ns
FA0	t_w(be[x]nV)		Write		N^⁽¹²⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Read		A^⁽¹⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Write		A^⁽¹⁾	ns
FA3	t_{d(csnV-advnIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE invalid	Read	-2+B^⁽²⁾	2+B^⁽²⁾	ns
FA3	t_{d(csnV-advnIV)}		Write	-2+B^⁽²⁾	2+B^⁽²⁾	ns
FA4	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Single read)	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+C^⁽³⁾	2+C^⁽³⁾	ns
FA9	t_d(aV-csnV)	Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+J^⁽⁹⁾	2+J^⁽⁹⁾	ns
FA10	t_{d(be[x]nV-csnV)}	Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+J^⁽⁹⁾	2+J^⁽⁹⁾	ns
FA12	t_{d(csnV-advnV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+K^⁽¹⁰⁾	2+K^⁽¹⁰⁾	ns
FA13	t_d(csnV-oenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+L^⁽¹¹⁾	2+L^⁽¹¹⁾	ns
FA16	t_w(aIV)	Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	G^⁽⁷⁾		ns
FA18	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Burst read)	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+I^⁽⁸⁾	2+I^⁽⁸⁾	ns
FA20	t_w(aV)	Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	D^⁽⁴⁾		ns
FA25	t_d(csnV-wenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+E^⁽⁵⁾	2+E^⁽⁵⁾	ns
FA27	t_{d(csnV-wenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn invalid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+F^⁽⁶⁾	2+F^⁽⁶⁾	ns
FA28	t_d(wenV-dV)	Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1		2	ns
FA29	t_d(dV-csnV)	Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2+J^⁽⁹⁾	2+J^⁽⁹⁾	ns
FA37	t_d(oenV-aIV)	Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1		2	ns

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(15) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-62 GPMC and NOR Flash — Asynchronous Read — Single Word