JAJSEE8G July   2014  – February 2018 DRV10983

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulators
        1. 8.3.1.1 Step-Down Regulator
        2. 8.3.1.2 3.3-V and 1.8-V LDO
      2. 8.3.2 Protection Circuits
        1. 8.3.2.1 Thermal Shutdown
        2. 8.3.2.2 Undervoltage Lockout (UVLO)
        3. 8.3.2.3 Overcurrent Protection (OCP)
        4. 8.3.2.4 Lock
      3. 8.3.3 Motor Speed Control
      4. 8.3.4 Sleep or Standby Condition
      5. 8.3.5 Non-Volatile Memory
    4. 8.4 Device Functional Modes
      1. 8.4.1  Motor Parameters
        1. 8.4.1.1 Motor Phase Resistance
        2. 8.4.1.2 BEMF Constant
      2. 8.4.2  Starting the Motor Under Different Initial Conditions
        1. 8.4.2.1 Case 1 – Motor Is Stationary
        2. 8.4.2.2 Case 2 – Motor Is Spinning in the Forward Direction
        3. 8.4.2.3 Case 3 – Motor Is Spinning in the Reverse Direction
      3. 8.4.3  Motor Start Sequence
        1. 8.4.3.1 ISD
        2. 8.4.3.2 Motor Resynchronization
        3. 8.4.3.3 Reverse Drive
        4. 8.4.3.4 Motor Brake
        5. 8.4.3.5 Motor Initialization
          1. 8.4.3.5.1 Align
          2. 8.4.3.5.2 Initial Position Detect (IPD)
            1. 8.4.3.5.2.1 IPD Operation
            2. 8.4.3.5.2.2 IPD Release Mode
            3. 8.4.3.5.2.3 IPD Advance Angle
          3. 8.4.3.5.3 Motor Start
        6. 8.4.3.6 Start-Up Timing
      4. 8.4.4  Start-Up Current Setting
        1. 8.4.4.1 Start-Up Current Ramp-Up
      5. 8.4.5  Closed Loop
        1. 8.4.5.1 Half Cycle Control and Full Cycle Control
        2. 8.4.5.2 Analog Mode Speed Control
        3. 8.4.5.3 Digital PWM Input Mode Speed Control
        4. 8.4.5.4 I2C Mode Speed Control
        5. 8.4.5.5 Closed Loop Accelerate
        6. 8.4.5.6 Control Coefficient
        7. 8.4.5.7 Commutation Control Advance Angle
      6. 8.4.6  Current Limit
        1. 8.4.6.1 Acceleration Current Limit
      7. 8.4.7  Lock Detect and Fault Handling
        1. 8.4.7.1 Lock0: Lock Detection Current Limit Triggered
        2. 8.4.7.2 Lock1: Abnormal Speed
        3. 8.4.7.3 Lock2: Abnormal Kt
        4. 8.4.7.4 Lock3 (Fault3): No Motor Fault
        5. 8.4.7.5 Lock4: Open Loop Motor Stuck Lock
        6. 8.4.7.6 Lock5: Closed Loop Motor Stuck Lock
      8. 8.4.8  AVS Function
        1. 8.4.8.1 Mechanical AVS Function
      9. 8.4.9  PWM Output
      10. 8.4.10 FG Customized Configuration
        1. 8.4.10.1 FG Output Frequency
        2. 8.4.10.2 FG Open-Loop and Lock Behavior
      11. 8.4.11 Diagnostics and Visibility
        1. 8.4.11.1 Motor Status Readback
        2. 8.4.11.2 Motor Speed Readback
          1. 8.4.11.2.1 Two-Byte Register Readback
        3. 8.4.11.3 Motor Electrical Period Readback
        4. 8.4.11.4 BEMF Constant Readback
        5. 8.4.11.5 Motor Estimated Position by IPD
        6. 8.4.11.6 Supply Voltage Readback
        7. 8.4.11.7 Speed Command Readback
        8. 8.4.11.8 Speed Command Buffer Readback
        9. 8.4.11.9 Fault Diagnostics
    5. 8.5 Register Maps
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Register Map
      3. 8.5.3 Register Definition
        1. Table 9. Register Description
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 ドキュメントの更新通知を受け取る方法
    6. 12.6 コミュニティ・リソース
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (DRV10983)
IVcc Supply current TA = 25°C; sleepDis = 1; SPEED = 0 V;
V(VCC) = 24 V; buck regulator		 3.5 5 mA
TA = 25°C; sleepDis = 1; SPEED = 0 V;
V(VCC) = 24 V; linear regulator		 11
IVccSTBY Standby current TA = 25°C; SPEED = 0 V; V(VCC) = 24 V;
standby mode device; buck regulator		 3 4 mA
TA = 25°C; SPEED = 0 V; V(VCC) = 24 V;
standby mode device; linear regulator		 9
SUPPLY CURRENT (DRV10983Z)
IVcc Supply current TA = 25°C; sleepDis = 1; SPEED = 0 V;
V(VCC) = 24 V; buck regulator		 3.5 5 mA
TA = 25°C; sleepDis = 1; SPEED = 0 V;
V(VCC) = 24 V; linear regulator		 11
IVccSLEEP Sleep current TA = 25°C; SPEED = 0 V; V(VCC) = 24 V;
sleep mode device; buck regulator		 160 200 µA
UVLO
VUVLO_R UVLO threshold voltage Rise threshold, TA = 25°C 7 7.4 8 V
VUVLO_F UVLO threshold voltage Fall threshold, TA = 25°C 6.7 7.1 7.5 V
VUVLO_HYS UVLO threshold voltage hysteresis TA = 25°C 200 300 400 mV
LDO OUTPUT
V3P3 V(VCC) = 24 V, TA = 25°C, VregSel = 0,
5-mA load		 3 3.3 3.6 V
V(VCC) = 24 V, TA = 25°C, VregSel = 1,
V(VREG)< 3.3 V, 5-mA load		 V(VREG) – 0.3 V(VREG) – 0.1 V(VREG)
V(VCC) = 24 V, TA = 25°C, VregSel = 1,
V(VREG) ≥ 3.3 V, 5-mA load		 3 3.3 3.6
IV3P3_MAX Maximum load from V3P3 V(VCC) = 24 V, TA = 25°C 5 mA
V1P8 V(VCC) = 24 V, TA = 25°C, VregSel = 0 1.6 1.78 2 V
V(VCC) = 24 V, TA = 25°C, VregSel = 1 1.6 1.78 2
STEP-DOWN REGULATOR
VREG Regulator output voltage TA = 25˚C; VregSel = 0, LSW = 47 µH,
CSW = 10 µF, Iload = 50 mA		 4.5 5 5.5 V
TA = 25˚C; VregSel = 1, LSW = 47 µH,
CSW = 10 µF, Iload = 50 mA		 3.06 3.4 3.6
VREG_L Regulator output voltage (linear mode) TA = 25°C, VregSel = 0, RSW = 39 Ω, CSW = 10 µF 5 V
TA = 25°C, VregSel = 1, RSW = 39 Ω, CSW = 10 µF 3.4
IREG_MAX Maximum load from VREG TA = 25°C, LSW = 47 µH, CSW = 10 µF 100 mA
INTEGRATED MOSFET
rDS(on) Series resistance (H + L) TA = 25˚C; V(VCC) = 24 V; V(VCP) = 29 V;
Iout = 1 A		 0.25 0.4 Ω
TA = 85˚C; V(VCC) = 24 V; V(VCP) = 29 V;
Iout = 1 A		 0.325
SPEED – ANALOG MODE
VAN/A_FS Analog full speed voltage V(V3P3) × 0.9 V
VAN/A_ZS Analog zero speed voltage 100 mV
tSAM Analog speed sample period 320 µs
VAN/A_RES Analog voltage resolution 5.8 mV
SPEED – PWM DIGITAL MODE
VDIG_IH PWM input high voltage 2.2 V
VDIG_IL PWM input low voltage 0.6 V
ƒPWM PWM input frequency 1 100 kHz
STANDBY MODE (DRV10983)
VEN_SB Analog voltage-to-enter standby mode SpdCtrlMd = 0 (analog mode) 30 mV
VEX_SB Analog voltage-to-exit standby SpdCtrlMd = 0 (analog mode) 120 mV
tEX_SB_ANA Time-to-exit from standby mode SpdCtrlMd = 0 (analog mode)
SPEED > VEX_SB 		700 ms
tEX_SB_DR_ANA Time taken to drive motor after exiting from standby mode SpdCtrlMd = 0 (analog mode)
SPEED > VEX_SL; ISDen = 0; BrkDoneThr[2:0] = 0		 1 µs
tEX_SB_PWM Time-to-exit from standby mode SpdCtrlMd = 1 (PWM mode)
SPEED > VDIG_IH 		1 µs
tEX_SB_DR_PWM Time taken to drive motor after exiting from standby mode SpdCtrlMd = 1 (PWM mode)
SPEED > VDIG_IH; ISDen = 0; BrkDoneThr[2:0] = 0 		55 ms
tEN_SB_ANA Time-to-enter sleep mode SpdCtrlMd = 0 (analog mode)
SPEED < VEN_SL; AvSIndEn = 0		 5 ms
tEN_SB_PWM Time-to-enter sleep mode SpdCtrlMd = 1 (PMW mode)
SPEED < VDIG_IL; AvSIndEn = 0		 60 ms
SLEEP MODE (DRV10983Z)
VEN_SL Analog voltage-to-enter sleep SpdCtrlMd = 0 (analog mode) 30 mV
VEX_SL Analog voltage-to-exit sleep SpdCtrlMd = 0 (analog mode) 2.2 3.3 V
tEX_SL_ANA Time-to-exit from sleep mode SpdCtrlMd = 0 (analog mode)
SPEED > VEX_SL 		1 µs
tEX_SL_DR_ANA Time taken to drive motor after exiting from sleep mode SpdCtrlMd = 0 (analog mode)
SPEED > VEX_SL; ISDen = 0; BrkDoneThr[2:0] = 0		 350 µs
tEX_SL_PWM Time-to-exit from sleep mode SpdCtrlMd = 1 (PWM mode)
SPEED > VDIG_IH 		1 µs
tEX_SL_DR_PWM Time taken to drive motor after exiting from sleep mode SpdCtrlMd = 1 (PWM mode)
SPEED > VDIG_IH; ISDen = 0; BrkDoneThr[2:0] = 0 		350 ms
tEN_SL_ANA Time-to-enter sleep mode SpdCtrlMd = 0 (analog mode)
SPEED < VEN_SL; AvSIndEn = 0		 5.2 ms
tEN_SL_PWM Time-to-enter sleep mode SpdCtrlMd = 1 (PMW mode)
SPEED < VDIG_IL; AvSIndEn = 0		 58 ms
RPD_SPEED_SL Internal SPEED pin pulldown resistance to ground VSPEED = 0 (sleep mode) 55 kΩ
DIGITAL I/O (DIR INPUT AND FG OUTPUT)
VDIR_H Input high 2.2 V
VDIR_L Input low 0.6 V
IFG_SINK Output sink current Vout = 0.3 V 5 mA
I2C SERIAL INTERFACE
VI2C_H Input high 2.2 V
VI2C_L Input low 0.6 V
LOCK DETECTION RELEASE TIME
tLOCK_OFF Lock release time 5 s
tLCK_ETR Lock enter time 0.3 s
OVERCURRENT PROTECTION
IOC_limit Overcurrent protection TA = 25˚C; phase to phase 3 4 A
THERMAL SHUTDOWN
TSDN Shutdown temperature threshold Shutdown temperature 150 °C
TSDN_HYS Shutdown temperature threshold Hysteresis 10 °C
BEMF COMPARATOR
BEMFHYS BEMF comparator hysteresis bemfHsyEn = 1 50 mV