JAJSTJ2 June   2024 DRV2911-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Stage
      2. 6.3.2 Hardware Interface
      3. 6.3.3 AVDD Linear Voltage Regulator
      4. 6.3.4 Step-Down Mixed-Mode Buck Regulator
        1. 6.3.4.1 Buck in Inductor Mode
        2. 6.3.4.2 Buck in Resistor mode
        3. 6.3.4.3 Buck Regulator with External LDO
        4. 6.3.4.4 AVDD Power Sequencing with Buck Regulator
        5. 6.3.4.5 Mixed mode Buck Operation and Control
        6. 6.3.4.6 Buck Undervoltage Lockout
        7. 6.3.4.7 Buck Overcurrent Protection
      5. 6.3.5 Charge Pump
      6. 6.3.6 Slew Rate Control
      7. 6.3.7 Cross Conduction (Dead Time)
      8. 6.3.8 Propagation Delay
      9. 6.3.9 Protections
        1. 6.3.9.1 PVDD Supply Undervoltage Lockout
        2. 6.3.9.2 AVDD Undervoltage Lockout
        3. 6.3.9.3 VCP Charge Pump Undervoltage Lockout
        4. 6.3.9.4 Overcurrent Latched Protection
        5. 6.3.9.5 Thermal Shutdown (OTSD)
          1. 6.3.9.5.1 OTSD FET
          2. 6.3.9.5.2 OTSD (Non-FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Reset Mode
        2. 6.4.1.2 Operating Mode
        3. 6.4.1.3 Fault Reset (RESETZ Pulse)
      2. 6.4.2 OUTOFF functionality
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Procedure
      2. 7.2.2 Voltage and Current Sense Circuitry
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

TJ = –40°C to +150°C, VPVDD = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES
IPVDDQPVDD sleep mode currentVPVDD > 6 V, RESETZ = 0, TA = 25 °C1.52.5µA
RESETZ = 02.55µA
IPVDDSPVDD standby mode currentVPVDD > 6 V, RESETZ = 1, PWMx = 0, IBK = 0, TA = 25 °C56mA
RESETZ = 1, PWMx = 0, IBK = 0610mA
IPVDDPVDD operating mode currentVPVDD > 6 V, RESETZ = 1, fPWM = 25 kHz, TA = 25 °C1113mA
VPVDD > 6 V, RESETZ = 1, fPWM = 200 kHz, TA = 25 °C1922mA
 RESETZ =1, fPWM = 25 kHz1217mA
 RESETZ =1, fPWM = 200 kHz1830mA
VAVDDAnalog regulator voltage0 mA ≤ IAVDD ≤ 30 mA3.13.33.465V
IAVDDExternal analog regulator load30mA
VVCPCharge pump regulator voltageVCP with respect to PVDD3.64.75.25V
tWAKEWakeup timeVPVDD > VUVLO, RESETZ = 1 to outputs ready and FAULTZ released1ms
tSLEEPSleep Pulse timeRESETZ = 0 period to enter sleep mode120µs
tRSTReset Pulse timeRESETZ = 0 period to reset faults2040µs
BUCK REGULATOR
VBK Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)		VPVDD > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to Hi-Z4.65.05.4V
VPVDD > 6.7 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin tied to AVDD5.25.75.8V
VPVDD < 6.0 V, 0 mA ≤ IBK ≤ 200 mAVPVDD–IBK*(RLBK+2)(1)V
VBKBuck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)		VPVDD > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to Hi-Z4.65.05.4V
VPVDD > 6.7 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin tied to AVDD5.25.75.8V
VPVDD < 6.0 V, 0 mA ≤ IBK ≤ 50 mAVPVDD–IBK*(RLBK+2)(1)V
VBKBuck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)		VPVDD > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to Hi-Z4.65.05.4V
VPVDD > 6.7 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin tied to AVDD5.25.75.8V
VPVDD  < 6.0 V, 0 mA ≤ IBK ≤ 40 mAVPVDD–IBK*(RBK+2)V
VBK_RIPBuck regulator ripple voltageVPVDD  > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck regulator with inductor, LBK = 47 uH, CBK = 22 µF–100100mV
VPVDD  > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with inductor, LBK = 22 uH, CBK = 22 µF–100100mV
VPVDD  > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with resistor; RBK = 22 Ω, CBK = 22 µF–100100mV
IBKExternal buck regulator loadLBK = 47 uH, CBK = 22 µF200 – IAVDDmA
LBK = 22 uH, CBK = 22 µF50 – IAVDDmA
RBK = 22 Ω, CBK = 22 µF40 – IAVDDmA
fSW_BKBuck regulator switching frequency Regulation Mode20535kHz
Linear Mode20535kHz
VBK_UVBuck regulator undervoltage lockoutVBK rising, VSEL_BK pin to Hi-Z2.72.82.9V
VBK falling, VSEL_BK pin to Hi-Z2.52.62.7V
VBK rising, VSEL_BK pin tied to AVDD4.24.44.55V
VBK falling, VSEL_BK pin tied to AVDD4.04.24.35V
VBK_UV_HYSBuck regulator undervoltage lockout hysteresisRising to falling threshold90200320mV
IBK_CLBuck regulator Current limit threshold360600900mA
IBK_OCPBuck regulator Overcurrent protection trip point234A
tBK_RETRYOvercurrent protection retry time0.711.3ms
LOGIC-LEVEL INPUTS (OUTOFF, PWMx, RESETZ)
VILInput logic low voltage00.6V
VIHInput logic high voltageOther Pins1.55.5V
RESETZ1.65.5V
VHYSInput logic hysteresisOther Pins180300420mV
RESETZ95250420mV
IILInput logic low currentVPIN (Pin Voltage) = 0 V–11µA
IIHInput logic high currentRESETZ, VPIN (Pin Voltage) = 5 V1030µA
Other pins, VPIN (Pin Voltage) = 5 V3075µA
RPDInput pulldown resistanceRESETZ150200300kΩ
Other pins70100130kΩ
CIDInput capacitance30pF
FOUR-LEVEL INPUTS (SLEW)
VL1Input mode 1 voltage (25V/μs)Tied to AGND00.2*AVDDV
VL2Input mode 2 voltage (50V/μs)Hi-Z0.27*AVDD0.5*AVDD0.545*AVDDV
VL3Input mode 3 voltage (125V/μs)47 kΩ +/- 5% tied to AVDD0.606*AVDD0.757*AVDD0.909*AVDDV
VL4Input mode 4 voltage (200V/μs)Tied to AVDD0.945*AVDDAVDDV
RPUInput pullup resistanceTo AVDD70100130kΩ
RPDInput pulldown resistanceTo AGND70100130kΩ
TWO-LEVEL INPUTS (VSEL_BK)
VL1 Input mode 1 voltage (5.0V) Hi-Z 0.27*AVDD 0.5*AVDD 0.545*AVDD V
VL2 Input mode 2 voltage (5.7V) Tied to AVDD 0.945*AVDD AVDD V
RPU Input pullup resistance To AVDD 70 100 130 kΩ
RPD Input pulldown resistance To AGND 70 100 130 kΩ
TWO-LEVEL INPUTS (OCP)
VL1 Input mode 1 voltage (16A limit) Tied to AGND 0 0.09*AVDD V
VL2 Input mode 2 voltage (24A limit) 22 kΩ ± 5% to AGND 0.12*AVDD 0.15*AVDD 0.55*AVDD V
RPU Input pullup resistance To AVDD 80 100 120 kΩ
RPD Input pulldown resistance To AGND 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (FAULTZ)
VOLOutput logic low voltageIOD = 5 mA0.4V
IOHOutput logic high currentVOD = 5 V–11µA
CODOutput capacitance30pF
DRIVER OUTPUTS
RDS(ON)Total MOSFET on resistance (High-side + Low-side)VPVDD > 6 V, IOUT = 1 A, TA = 25°C95120mΩ
VPVDD < 6 V, IOUT = 1 A, TA = 25°C105130mΩ
VPVDD > 6 V, IOUT = 1 A, TJ = 150 °C140185mΩ
VPVDD < 6 V, IOUT = 1 A, TJ = 150 °C145190mΩ
SRPhase pin slew rate switching low to high (Rising from 20 % to 80 %)
 		VPVDD = 24 V, SLEW pin tied to AGND142545V/µs
VPVDD = 24 V, SLEW pin to Hi-Z305080V/µs
VPVDD = 24 V, SLEW pin to 47 kΩ +/- 5% to AVDD80125185V/µs
VPVDD = 24 V, SLEW pin tied to AVDD130200280V/µs
SRPhase pin slew rate switching high to low (Falling from 80 % to 20 %)
 		VPVDD = 24 V, SLEW pin tied to AGND142545V/µs
VPVDD = 24 V, SLEW pin to Hi-Z305080V/µs
VPVDD = 24 V, SLEW pin to 47 kΩ +/- 5% to AVDD80125185V/µs
VPVDD = 24 V, SLEW pin tied to AVDD110200280V/µs
ILEAKLeakage current on OUTxVOUTx = VPVDD, RESETZ = 15mA
Leakage current on OUTx VOUTx = 0 V, RESETZ = 11µA
tDEADOutput dead time (high to low / low to high)VPVDD = 24 V, SR = 25 V/µs, HS driver OFF to LS driver ON and LS driver OFF to HS driver ON18003400ns
VPVDD = 24 V, SR = 50 V/µs, HS driver OFF to LS driver ON and LS driver OFF to HS driver ON11001550ns
VPVDD = 24 V, SR = 125 V/µs, HS driver OFF to LS driver ON and LS driver OFF to HS driver ON6501000ns
VPVDD = 24 V, SR = 200 V/µs, HS driver OFF to LS driver ON and LS driver OFF to HS driver ON500750ns
tPDPropagation delay (high-side / low-side ON/OFF)VPVDD = 24 V, INHx/INLx = 1 to OUTx transition, SR = 25 V/µs20004550ns
VPVDD = 24 V, INHx/INLx = 1 to OUTx transition, SR = 50V/µs12002150ns
VPVDD = 24 V, INHx/INLx = 1 to OUTx transition, SR = 125 V/µs8001350ns
VPVDD = 24 V, INHx/INLx = 1 to OUTx transition, SR = 200 V/µs6501050ns
tMIN_PULSEMinimum output pulse width
SR = 200 V/µs

600ns
PROTECTION CIRCUITS
VUVLOSupply undervoltage lockout (UVLO)PVDD rising4.34.44.5V
PVDD falling4.14.24.3V
VUVLO_HYSSupply undervoltage lockout hysteresisRising to falling threshold140200350mV
tUVLOSupply undervoltage lockout deglitch time357µs
VCPUVCharge pump undervoltage lockout (above PVDD)Supply rising2.32.52.7V
Supply falling2.22.42.6V
VCPUV_HYSCharge pump UVLO hysteresisRising to falling threshold75100140mV
VAVDD_UVAnalog regulator undervoltage lockoutSupply rising2.72.853V
Supply falling2.52.652.8V
VAVDD_UV_HYSAnalog regulator undervoltage lockout hysteresisRising to falling threshold180200240mV
IOCPOvercurrent protection trip pointOCP pin tied to AGND101622A
IOCPOvercurrent protection trip pointOCP pin tied to 22 kΩ ±5% to AGND152430A
tOCPOvercurrent protection deglitch time0.060.30.6µs
tRETRYOvercurrent protection retry time456ms
TOTWThermal warning temperatureDie temperature (TJ)135145155°C
TOTW_HYSThermal warning hysteresisDie temperature (TJ)152026°C
TTSDThermal shutdown temperature Die temperature (TJ)170180190°C
TTSD_HYSThermal shutdown hysteresis Die temperature (TJ)152025°C
TTSD_FETThermal shutdown temperature (FET)Die temperature (TJ)165175187°C
TTSD_FET_HYSThermal shutdown hysteresis (FET)Die temperature (TJ)182530°C
(1) RLBK is resistance of inductor LBK