JAJSHW2A August   2019  – April 2020 DRV425-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fluxgate Sensor Front-End
        1. 8.3.1.1 Fluxgate Sensor
        2. 8.3.1.2 Bandwidth
        3. 8.3.1.3 Differential Driver for the Internal Compensation Coil
        4. 8.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
      2. 8.3.2 Shunt-Sense Amplifier
      3. 8.3.3 Voltage Reference
      4. 8.3.4 Low-Power Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Linear Position Sensing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Current Sensing in Busbars
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Decoupling
    2. 10.2 Power-On Start-Up and Brownout
    3. 10.3 Power Dissipation
      1. 10.3.1 Thermal Pad
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

all minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA (unless otherwise noted); typical values are at VDD = 5.0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FLUXGATE SENSOR FRONT-END
Offset No magnetic field –8 ±2 8 µT
Offset drift No magnetic field ±5 nT/°C
G Gain Current at DRV1 and DRV2 outputs 12.2 mA/mT
Gain error ±0.04%
Gain drift Best-fit line method ±7 ppm/°C
Linearity error 0.1%
Hysteresis Magnetic field sweep from –10 mT to 10 mT 1.4 µT
Noise f = 0.1 Hz to 10 Hz 17 nTrms
Noise density f = 1 kHz 1.5 nT/√Hz
Compensation range –2 2 mT
Saturation trip level for the
ERROR pin(2) 		Open-loop, uncompensated field 1.6 mT
ERROR delay Open-loop at B > 1.6 mT 4 to 6 µs
BW Bandwidth BSEL = 0, RSHUNT = 22 Ω 32 kHz
BSEL = 1, RSHUNT = 22 Ω 47
IOS Short-circuit current VDD = 5 V 250 mA
VDD = 3.3 V 150
Common-mode output voltage at the DRV1 and DRV2 pins VREFOUT V
Compensation coil resistance 100 Ω
SHUNT-SENSE AMPLIFIER
VOO Output offset voltage VAINP = VAINN = VREFIN, VDD = 3.0 V –0.075 ±0.01 0.075 mV
Output offset voltage drift –2 ±0.4 2 µV/°C
CMRR Common-mode rejection ratio, RTO(1) VCM = –1 V to VDD + 1 V, VREFIN = VDD / 2 –250 ±50 250 µV/V
PSRRAMP Power-supply rejection ratio, RTO(1) VDD = 3.0 V to 5.5 V, VCM = VREFIN –86 ±4 86 µV/V
VICR Common-mode input voltage range –1 VDD + 1 V
zid Differential input impedance 16.5 20 23.5 kΩ
zic Common-mode input impedance 40 50 60 kΩ
Gnom Nominal gain VVOUT / (VAINP – VAINN) 4 V/V
EG Gain error –0.3% ±0.02% 0.3%
Gain error drift –5 ±1 5 ppm/°C
Linearity error 12 ppm
Voltage output swing from negative rail (OR pin trip level)(2) VDD = 5.5 V, IVOUT = 2.5 mA 48 85 mV
VDD = 3.0 V, IVOUT = 2.5 mA 56 100
Voltage output swing from positive rail (OR pin trip level)(2) VDD = 5.5 V, IVOUT = –2.5 mA VDD – 85 VDD – 48 mV
VDD = 3.0 V, IVOUT = –2.5 mA VDD – 100 VDD – 56
Signal overrange indication delay
(OR pin)(2) 		VIN = 1-V step 2.5 to 3.5 µs
IOS Short-circuit current VOUT connected to GND –18 mA
VOUT connected to VDD 20
BW–3dB Bandwidth 2 MHz
SR Slew rate 6.5 V/µs
tsa Settling time Large signal ΔV = ± 2 V to 1%, no external filter 0.9 µs
Small signal ΔV = ± 0.4 V to 0.01% 8
en Output voltage noise density f = 1 kHz, compensation loop disabled 170 nV/√Hz
VREFIN Input voltage range at pin REFIN Input voltage range at REFIN pin GND VDD V
VOLTAGE REFERENCE
VREFOUT Reference output voltage at the REFOUT pin RSEL[1:0] = 00, no load 2.45 2.5 2.55 V
RSEL[1:0] = 01, no load 1.6 1.65 1.7
RSEL[1:0] = 1x, no load 45 50 55 % of VDD
Reference output voltage drift RSEL[1:0] = 0x –50 ±10 50 ppm/°C
Voltage divider gain error drift RSEL[1:0] = 1x –50 ±10 50 ppm/°C
PSRRREF Power-supply rejection ratio RSEL[1:0] = 0x –300 ±15 300 µV/V
ΔVO(ΔIO) Load regulation RSEL[1:0] = 0x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C		 0.15 0.35 mV/mA
RSEL[1:0] = 1x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C		 0.3 0.8
IOS Short-circuit current REFOUT connected to VDD 20 mA
REFOUT connected to GND –18 mA
DIGITAL INPUTS/OUTPUTS (CMOS)
IIL Input leakage current 0.01 µA
VIH High-level input voltage TA = –40°C to +125°C 0.7 × VDD VDD + 0.3 V
VIL Low-level input voltage TA = –40°C to +125°C –0.3 0.3 × VDD V
VOH High-level output voltage Open-drain output Set by external pullup resistor V
VOL Low-level output voltage 4-mA sink current 0.3 V
POWER SUPPLY
IQ Quiescent current IDRV1/2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V,
TA = –40°C to +125°C		 6 8 mA
IDRV1/2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V,
TA = –40°C to +125°C		 7 10
VPOR Power-on reset threshold 2.4 V
(1) Parameter value is referred-to-output (RTO).
(2) See the Magnetic Field Range, Overrange Indicator, and Error Flag section for details on the behavior of the ERROR and OR outputs.