The DRV7308 controls the state of the GaN FET based on the PWM input signals at the INHx and INLx pins. The device uses the BRAKE signal to apply brake to motor drive. A logic high at the BRAKE signal overrides the INHx and INLx pins and turns on all low side GaN transistors. The device enters shutoff mode (all the gate drivers and GaN FETs in off state) and ignores the status of the INHx, INLx, and BRAKE pins when a logic low on the EN pin occurs. A 20-40μs logic low pulse at the EN pin resets the device from OCP and OTP faults. The truth table for the input control logic is shown in Table 12-2.