The bulk capacitor must be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths must be as wide as possible and numerous vias must be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Small-value capacitors such as the GVDD decoupling capacitor, high frequency capacitor on VM pin to PGND, and the bootstrap capacitors must be placed close to device pins.

To minimize the power loop area, place the shunt resistors close to the device SLx pins and use copper polygon on the end of the shunt resistor, and return the current pack to the decoupling capacitor on the VM pin with a wider trace on the top layer, or through a copper polygon on the bottom layer with a sufficient number of stitching vias.

To improve thermal performance, maximize the copper planes on OUTx and PGND nets. To maximize the thermal performance, use multiple stitching vias on the OUTx pads and PGND pads and use larger copper planes on the top and bottom layers, as shown in the Figure 13-1.

The decoupling capacitor on the VM pin can be connected to any one side VM pin or to both the pins. The VM pins are internally shorted in the device and there is no need to short externally on the PCB.