Below is the block diagram for the electrochromic driver:

Figure 7-8 Electro-chromic Driver Block Diagram - Default Configuration

Depending on the system implementation, the device electrochrome driver supports configuration where the drain of electrochrome high-side charge MOSFET can be supplied from either high-side driver OUT11, or directly from the supply voltage (PVDD). The EC control block can operate independently of the supply, with independent protection circuits in either configuration. This can be useful if an extra high-side driver is needed to drive another load. The main limitation in this configuration is that if the charge MOSFET fails short, the connection to supply cannot be shut off as when OUT11 is used as EC supply. A short and open-load condition can still be detected when EC supplied with PVDD directly (OUT11 is configured as independent).

OUT11 for EC supply: This configuration is set in register HS_OC_CNFG, bit OUT11_EC_MODE. By default, OUT11_EC_MODE = 1b, which is configured as the supply for EC drive as shown in the block diagram above. When in this configuration, bits OUT11_CNFG in register HS_HEAT_OUT_CNFG are ignored (ON/OFF, SPI/PWM). Both OUT11 and the 1.5-Ω ECFB low-side discharge MOSFET have overcurrent and open load detection active during EC charge and discharge states, respectfully.

PVDD for EC supply, independent OUT11:To use OUT11 as an independent high-side driver (independent of EC control) to drive a separate load, where the drain of the EC charge MOSFET is connected directly to supply voltage, set OUT11_EC_MODE = 0b in register HS_OC_CNFG. In this configuration, there is short to battery, short to ground, and open load detection on ECFB that can be independently enabled during EC charge state, replacing the diagnostics of OUT11. As before, the ECFB low-side discharge MOSFET protection circuits are active during EC discharge state. The diagram below shows this configuration:

To enable the EC driver: Set bits EC_ON and EC_V_TAR to the desired target voltage in register HS_EC_HEAT_CTRL to enable the EC driver control loop. Once these bits are set, EC driver control loop is enabled.

For EC element voltage control: Once the EC driver is enabled, the feedback loop of the driver is activated, and regulates ECFB pin voltage to the target voltage set in bits EC_V_TAR in register HS_EC_HEAT_CTRL. The target voltage on ECFB pin is binary coded with a full-scale range of either 1.5 V or 1.2 V, depending if bit ECFB_MAX in register EC_CNFG is set to 1 or 0, respectively. ECFB_MAX = 0b is the default value (1.2 V).

Whenever a new value for the EC voltage is set, there is a blanking time t_{BLK_ECFB} of 250 μs for ECFB_HI or ECFB_LO status indication of ECFB once the control loop begins regulation to the new target value.

The device provides two discharge modes: fast discharge and PWM discharge.

Fast discharge of the EC element: To fully discharge the EC element with fast discharge, the target output voltage EC_V_TAR must be set to '0b', and bits ECFB_LS_EN and EC_ON must be set to '1b'. When these three conditions are met, the voltage at pin ECFB is discharged by pulling the internal 1.5-Ω low-side MOSFET on ECFB pin to ground.

1. Configure ECFB_LS_PWM = 0b in register EC_CNFG
2. Set bits ECFB_LS_EN = 1b, EC_ON = 1b and EC_V_TAR = 0b in register HS_EC_HEAT_CTRL.
3. ECFB LS MOSFET is enabled and performs fast discharge of EC mirror.

PWM discharge of the EC element: The steps below outline the PWM discharge cycle of electrochrome driver:

1. Configure ECFB_LS_PWM = 1b in register EC_CNFG
2. Set bits ECFB_LS_EN = 1b, EC_ON = 1b, EC_V_TAR = 0b in register HS_EC_HEAT_CTRL.
3. If the regulation loop detects V_ECDRV is less than V_ECFB for longer than t_RECHARGE or 3ms, the ECDRV regulator is switched off and the LS MOSFET on ECFB is activated for ~300 ms (t_DISCHARGE). During this discharge, the ECDRV output is pulled low to prevent shoot-thru currents.
4. At the end of the discharge pulse t_DISCHARGE, the discharge MOSFET is switched off and the regulation loop is activated again with the new lower value. The regulation loop goes back to step 2, and out of regulation is again observed (V_ECDRV - V_ECFB).

The diagram below shows the PWM discharge cycle of the electrochrome driver:

Figure 7-9 Electrochrome Discharge with PWM

The status of the voltage control loop is reported via SPI and should be observed to determine EC charge and discharge control timing. If the voltage at pin ECFB is higher than the target value, then bit ECFB_HI is set. If the voltage at pin ECFB is lower than the target value, ECFB_LO is set. Both status bits are valid if they are stable for at least the filter time t_{FT_ECFB}. The bits are not latched, and are not assigned as global faults.

Exit discharge mode: To exit discharge mode, ECFB_LS_EN must be de-asserted. If ECFB_LS_EN bit is left high when a new target voltage is programmed, the control loop will not respond since internal logic prevents both OUT11 and ECFB LS from being simultaneously on.

A capacitor of at least 4.7 nF has to be added to pin ECDRV, and 220 nF capacitor between ECFB and ground to increase control loop stability. For noise immunity reasons, it is recommended to place the loop capacitors as close as possible to the respective pins.

If the EC driver is not used, connect ECFB pin to ground.