SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.2.1.3 OUT7 HS ITRIP Behavior

For OUT7 in low-RDSON mode, there is a fixed frequency current regulation feature called HS ITRIP that can be used to restart the driver if over current occurs. This ITRIP feature (separate from ITRIP for half-bridges) is available for OUT7 (and EC driver) of the high-side drivers, and intended for loads which have inrush currents that are higher than the over current protection threshold of a driver, such as a lamp or bulb.

It is important to note that in order for HS ITRIP to work, OUT7 OCP must be disabled.

If bit OUT7_ITRIP_CNFG bits are non-zero, and the load current on OUT7 exceeds IOC7 threshold, ITRIP regulation takes place. The status bit is OUT7_ITRIP_STAT in register EC_HEAT_ITRIP_STAT is asserted depending on OUT7_ITRIP_CNFG configuration.

There is also an optional OUT7 ITRIP timeout feature. Depending on OUT7_ITRIP_CNFG settings, OUT7 or ITRIP regulation can be disabled after timeout is exceeded. For OUT7_ITRIP_CNFG = 01b, OUT7 is disabled if ITRIP regulation time tOUT7_ITRIP occurs for longer than the configured timeout tOUT7_ITRIP_TO. For OUT7_ITRIP_CNFG = 11b, ITRIP Regulation is disabled if ITRIP regulation time tOUT7_ITRIP occurs for longer than the configured timeout tOUT7_ITRIP_TO. In both cases, the status bit OUT7_ITRIP_TO is latched. Bits OUT7_ITRIP_CNFG is located in register HS_REG_CNFG1. If it is desirable to have OUT7 ITRIP regulation occur indefinitely, set OUT7_ITRIP_CNFG = 10b.

The table below summarizes the regulation, status and fault behavior of OUT7 ITRIP.

Table 7-13 OUT7 ITRIP Configuration and Status Summary
OUT7_ITRIP_CNFG[1] OUT7_ITRIP_CNFG[0] Mode Description OUT7_ITRIP_STAT ITRIP Stat Fault Clear OUT7_ITRIP_TO ITRIP Timeout Fault Clear
0b 0b No ITRIP regulation Latches when OUT7 overcurrent threshold exceeded CLR_FLT command Timeout disabled n/a
0b 1b ITRIP regulation Latches after timeout CLR_FLT command. Auto-clears if previously latched. Latched after timeout limit reached. CLR_FLT restarts the driver if disabled.
1b 0b Safe Retry with ITRIP regulation Latches when OUT7 overcurrent threshold exceeded CLR_FLT restarts the driver with regulation. Timeout disabled n/a
1b 1b ITRIP regulation with timeout and regulation disable Latches after timeout limit reached. After fault clear, re-latches if OUT7 overcurrent threshold still exceeded CLR_FLT command. Auto-clear at start. Latched after timeout limit reached. CLR_FLT restarts the regulation if disabled.

The table below summarizes time limit options:

Table 7-14 OUT7 ITRIP Timeout Options
ITRIP_TO_SEL Timeout Time
00b 100 ms
01b 200 ms
10b 250 ms
11b 290 ms

HS ITRIP mode is disabled as the default setting for OUT7. To set OUT7 in HS ITRIP mode:

  1. Configure OUT7 for low-RDSON mode by setting bit OUT7_RDSON_MODE = 1 in register HS_OC_CNFG.
  2. Enable and configure OUT7 ITRIP by setting bits OUT7_ITRIP_CNFG = 1Xb in register HS_REG_CNFG1 per the OUT7 ITRIP configuration summary table.
  3. If timeout is used, configure timeout limit with ITRIP_TO_SEL bits in HS_REG_CNFG1.
  4. Set ITRIP timing parameters. ITRIP frequency, blanking and deglitch configured with bits OUT7_ITRIP_FREQ, OUT7_ITRIP_BLK and OUT7_ITRIP_DG in register HS_REG_CNFG1.
  5. Disable OCP for OUT7 with bit OUT7_OCP_DIS in register HS_REG_CNFG1.
Table 7-15 OUT7 ITRIP Frequency Option Summary
Frequency (fITRIP_HS) OUT7_ITRIP_FREQ
1.7 kHz 00b
2.2 kHz 01b
3 kHz 10b
4.4 kHz 11b
Table 7-16 OUT7 ITRIP Blanking Option Summary
Blanking Time (tITRIP_HS_BLK) OUT7_ITRIP_BLK
RSVD 00b
0 μs 01b
20 μs 10b
40 μs 11b
Table 7-17 OUT7 ITRIP Deglitch Option Summary
Deglitch Time (tITRIP_HS_DG) OUT7_ITRIP_DG
48 μs 00b
40 μs 01b
32 μs 10b
24 μs 11b

The ITRIP deglitch timer starts when the OUT7 ITRIP blank time expires. The minimum OUT7 ITRIP ON time is the sum of blanking and deglitch times, and total period is determined by the OUT7 ITRIP frequency. The diagram below shows the ITRIP behavior for OUT7.

DRV8000-Q1 OUT7 ITRIP Behavior with Incandescent Bulb Figure 7-5 OUT7 ITRIP Behavior with Incandescent Bulb

The recovery activation sequence for OUT7 in HS ITRIP mode has three configurable timing parameters:

  • tOUT7_ITRIP_FREQ (1/TOUT7_ITRIP_FREQ)
  • tOUT7_ITRIP_BLK
  • tOUT7_ITRIP_DG

The blanking time tOUT7_ITRIP_BLK is default 40 μs (typ), after which the over current condition can be detected. tOUT7_ITRIP_DG is the time OUT7 remains on after over current protection threshold is exceeded. TOUT7_ITRIP_FREQ is the time period of the ITRIP loop, inverse of tOUT7_ITRIP_FREQ. These settings are configurable in register HS_REG_CNFG1.