SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.7.8 Fault Detection and Response Summary Table

Table 7-47 Fault Detection and Response Summary
NAMECONDITIONSPI BITMODEDIGITAL CORECHARGE PUMP DRIVERSCURRENT SENSERESPONSE
Disable Gate Driver DRVOFF = High or
EN_GD = 0b		 n/a n/a Active Active Pull Down Active n/a
SPI Clock FaultInvalid SPI Clock FrameSCLK_FLTLatchedActiveActiveActiveActiveSPI_ERR, SPI, Reject Frame
DVDD Power-on-ResetDVDD < VDVDD_PORPORn/aResetDisabledSemi-Active
Pull Down		DisabledSPI
PVDD UndervoltagePVDD < VPVDD_UVPVDD_UVLatchedActiveDisabledSemi-Active
Pull Down		DisabledSPI
AutomaticActiveDisabledSemi-Active
Pull Down		DisabledSPI
PVDD OvervoltagePVDD > VPVDD_OVPVDD_OVLatchedActiveActivePull DownActiveSPI
PVDD_OVAutomaticActiveActivePull DownActiveSPI
PVDD_OVWarningActiveActiveActiveActiveWARN, SPI
n/aDisabledActiveActiveActiveActiven/a
VCP UndervoltageVCP < VVCP_UVVCP_UVLatchedActiveDisabledSemi-Active
Pull Down		DisabledSPI
AutomaticActiveActiveSemi-Active
Pull Down		DisabledSPI
VDS Overcurrent VDS > VVDS_LVL GD, VDS_X Latched Active Active IVDS_IDRVN
Pull Down		 Active SPI
Cycle Active Active IVDS_IDRVN
Pull Down		 Active SPI
Warning Active Active Active Active WARN, SPI
Disabled Active Active Active Active n/a
VGS Gate Fault VGS > VVGS_LVL GD, VGS_X Latched Active Active Pull Down Active SPI
Cycle Active Active Pull Down Active SPI
Warning Active Active Active Active WARN, SPI
Disabled Active Active Active Active n/a
Offline Open Load n/a VDS_X MCU Active Active Pull Down Active SPI
Offline Short Circuit n/a VDS_X MCU Active Active Pull Down Active SPI
Half-bridge Overcurrent Fault (OUT1-OUT6) IOUTx > IOCPx HB, OUTx_HS_OCP, OUTx_LS_OCP Latched Active Active Affected driver Hi-Z Active SPI
Half-bridge active open load Fault (OUT1-OUT6) IOUTx < IOLP_OUTx HB, OUTx_OLA Latched Active Active Active Active WARN
Half-bridge passive open load Fault (OUT1-OUT6) IOUTx < IOLP_OUTx HB, HB_OLP_STAT Live Active Active n/a Active WARN
High-side Driver overcurrent Fault (OUT7-OUT12) IOUTx > IOCPx HS, OUTx_OCP Latched Active Active Affected driver Hi-Z Active SPI
High-side Driver OUT7 ITRIP IOUT7 > IOC7 ITRIP, OUT7_ITRIP_STAT Warning Active Active n/a Active WARN
tOUT7_ITRIP > tOUT7_ITRIP_TO HS, ITRIP, OUT7_ITRIP_TO, OUT7_ITRIP_STAT Latched Active Active OUT7 Hi-Z after timeout Active SPI
IOUT7 > IOC7 ITRIP, OUT7_ITRIP_STAT Warning Active Active OUT7 ITRIP regulation indefinite Active WARN
tOUT7_ITRIP > tOUT7_ITRIP_TO ITRIP, OUT7_ITRIP_TO, OUT7_ITRIP_STAT Warning Active Active OUT7 ITRIP regulation disabled; Active WARN
High-side Driver open load Fault (OUT7-OUT12) IOUTx < IOCPx HS, OUTx_OLP Warning Active Active Active Active WARN
ECFB Overvoltage VECFB>VECFB_OV EC_HEAT, ECFB_OV Disabled Active Active n/a Active n/a
VECFB>VECFB_OV EC_HEAT, ECFB_OV Latched Active Active n/a Active SPI
VECFB>VECFB_OV EC_HEAT, ECFB_OV Latched Active Active ECDRV pulled down, ECFB LS FET Hi-Z Active SPI
ECFB Undervoltage VECFB>VECFB_UV EC_HEAT, ECFB_UV Disabled Active Active n/a Active n/a
VECFB>VECFB_UV EC_HEAT, ECFB_UV Latched Active Active n/a Active SPI
VECFB>VECFB_UV EC_HEAT, ECFB_UV Latched Active Active ECDRV pulled down, ECFB LS FET Hi-Z Active SPI
ECFB Above Target Voltage VECFB>VEC_V_TAR EC_HEAT, ECFB_HI Live Active Active n/a Active WARN
ECFB Below Target Voltage VECFB<VEC_V_TAR EC_HEAT, ECFB_LO Live Active Active n/a Active WARN
ECFB Overcurrent (discharge) IECFB> IECFB_OC EC_HEAT, ECFB_OC Latched Active Active ECFB Hi-Z Active SPI
ECFB Open load (discharge) IECFB< IOL_ECFB_LS EC_HEAT, ECFB_OL Latched Active Active n/a Active WARN, SPI
ECFB Open load (active/charge, OUT11 independent mode, ECDRV_OL_EN enabled) VECFB> VECFB_OV EC_HEAT, ECFB_OL, ECFB_OV Latched Active Active n/a Active WARN, SPI
Heater VDS Overcurrent Fault VHEAT_VDS > VHEAT_VDS_LVL EC_HEAT, HEAT_VDS Latched Active Active Pull down Active SPI
Cycle Active Active Pull Down Active SPI
Warning Active Active Active Active WARN, SPI
Disabled Active Active Active Active n/a
Heater VDS Open load Fault VSH_HS > VOL_HEAT EC_HEAT, HEAT_OL Latched Active Active Pull down Active SPI
Zone X Thermal WarningTJ > TOTW_XOTW, ZONEx_OTW_XAutomaticActiveActiveActiveActiveWARN, SPI
Zone X Thermal ShutdownTJ > TOTSDOTSD, ZONEx_OTSDLatchedActiveDisabledSemi-Active
Pull Down, Hi-Z		DisabledSPI
WatchdogInvalid Access or ExpirationWD_FLTWarningActiveActiveActiveActiveWARN, SPI
Latched FaultActiveActivePull DownActiveSPI