SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)

The user can determine the impedance on a pair of half-bridges using off-state diagnostics while the half-bridges are disabled in register HB_OUT_CNFGx. With this diagnostic, it is possible to detect the following fault conditions passively:

  • Output short to VM or GND < 1000 Ω
  • Open load > 1.5K Ω for high-side load, VM = 13.5 V

Note: It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this logically if an over current fault (OCP) occurs when an output is actively driven, but OLP diagnostics do not report any fault in the when the output is disabled. Occurrence of both OCP when an output is actively drive and OLP when the output is disabled would imply a terminal short (short on selected output node).

  • The user can configure the following combinations
    • Internal pull up resistor (ROLP_PU) on OUTx
    • Internal pull down resistor (ROLP_PD) on OUTx
    • Comparator reference level
  • This combination is determined by the HB_OLP_CNFG bits in the HB_OL_CNFG1 register.
  • The half-bridge pairs to be diagnosed are determined by the HB_OLP_SEL bits in the HB_OL_CNFG1 register.
  • The off-state diagnostics comparator output is available on HB_OLP_STAT bit in HB_STAT2 register. The output is not latched.
  • The user is expected to toggle through all the combinations and record the status bit output after its output is settled.
  • Based on the input combinations and status register, the user can determine if there is a fault on the output.

DRV8000-Q1 Off-State (Passive) Diagnostics Figure 7-14 Off-State (Passive) Diagnostics

The following output, pull-down/pull-up and VREF combinations are shown below:

Table 7-33 Off-state Output Pull-up/pull-down and VREF Options
HB_OLP_CNFG Description
00b OLP Off
01b Output X Pull-up enabled, Output Y pull-down enabled, Output Y selected, VREF Low
10b Output X Pull-up enabled, Output Y pull-down enabled, Output X selected, VREF High
11b Output X Pull-down enabled, Output Y pull-up enabled, Output Y selected, VREF Low

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load is shown in Table 7-34 For the diagnostics to be active and valid, all half-bridge configurations in bits OUTx_CNFG in registers HB_OUT_CNFGx must be zero (disabled).

Table 7-34 Off-State Diagnostics Control Table
User Inputs OLP Set-Up HB_OLP_STAT
HB_OLP_CNFG nSLEEP OUTX OUTY CMP REF Output Selected Normal Open Short VM Short
2'b01 1 ROLP_PU ROLP_PD VOLP_REFL OUTY 1b 0b 0b 1b
2'b10 1 ROLP_PU ROLP_PD VOLP_REFH OUTX 0b 1b 0b 1b
2'b11 1 ROLP_PD ROLP_PU VOLP_REFL OUTY 1b 1b 0b 1b

The following half-bridge pair off-state combinations and selection values are shown below.

Note: If any half-bridge is enabled, then all half-bridge OLP bits will be automatically disabled (0b).

Table 7-35 OUTx & OUTy Configurations
HB_OLP_SEL OUTX & OUTY Pairs Selected
0000b No output
0001b OUT1 & OUT2
0010b OUT1 & OUT3
0011b OUT1 & OUT4
0100b OUT1 & OUT5
0101b OUT1 & OUT6
0110b OUT2 & OUT3
0111b OUT2 & OUT4
1000b OUT2 & OUT5
1001b OUT2 & OUT6
1010b OUT3 & OUT4
1011b OUT3 & OUT5
1100b OUT3 & OUT6
1101b OUT4 & OUT5
1110b OUT4 & OUT6
1111b OUT5 & OUT6