SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.5.2.1 Smart Gate Driver

The DRV8000-Q1 provides an advanced, adjustable floating smart gate driver architecture to provide fine MOSFET control and robust switching performance. The smart gate driver architecture offers driver functions for slew rate control and a driver state machine for dead-time handshaking, parasitic dV/dt gate coupling prevention, and MOSFET gate fault detection.

Advanced adaptive drive functions are provided for reducing propagation delay, reducing duty cycle distortion, and closed loop programmable slew time. The advanced smart gate driver functions are only available in the Section 7.4.4.1 and PH/EN mode. The advanced functions do not interfere with standard operation of the gate drivers and can be utilized as needed by system requirements.

The different functions of the smart gate drive architecture are summarized below with additional details in the following sections.

Smart Gate Driver Core Functions:

Note: The advanced, adaptive drive functions and registers are not required for normal operation of the device and intended for specific system requirements.
Table 7-43 Smart Gate Driver Terminology Descriptions
Core Function Terminology Description
IDRIVE / TDRIVE IDRVP Programmable gate drive source current for adjustable MOSFET slew rate control. Configured with the IDRVP_x control register.
IDRVN Programmable gate drive sink current for adjustable MOSFET slew rate control. Configured with the IDRVN_x control register.
IHOLD Fixed gate driver hold pull up current during non-switching period.
ISTRONG Fixed gate driver strong pull down current during non-switching period.
tDRIVE IDRVP/N drive current duration before IHOLD or ISTRONG. Also provides VGS and VDS fault monitor blanking period. Configured with the VGS_TDRV control register.
tPD Propagation delay from logic control signal to gate driver output change.
tDEAD Body diode conduction period between high-side and low-side switch transition. Configured with the VGS_TDEAD control register.
PDR
(Pre-charge)		 ICHR_INIT Gate drive source current initial value for charge control loop. Configured with the PRE_CHR_INIT control register
IPRE_CHR Gate drive source current for pre-charge period after control loop lock. Adjustment rate configured with the KP_PDR control register. Max current clamp configured with the PRE_MAX control register.
tPRE_CHR Gate drive source current pre-charge period duration. Configured with the T_PRE_CHR control register.
tDON Delay time from start of pre-charge period to rising VSH crossing VSH_L threshold. Configure with T_DON_DOFF control register.
IDCHR_INIT Gate drive sink current initial value for discharge period control loop. Configured with the PRE_DCHR_INIT control register.
IPRE_DCHR Gate drive sink current for pre-discharge period after control loop lock. Adjustment rate configured with the KP_PDR control register. Max current clamp configured with the PRE_MAX control register.
tPRE_DCHR Gate drive sink current pre-discharge period duration. Configured with the T_PRE_DCHR control register.
tDOFF Delay time from start of pre-discharge period to falling VSH crossing VSH_H threshold. Configure with T_DON_DOFF control register.
VSH_L Low voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
VSH_H High voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
PDR
(Post-charge)		 IPST_CHR Gate drive source current for post-charge period. Adjustment rate configured with the KP_PST control register.
tPST_CHR Gate drive source current post-charge period duration.
IPST_DCHR Gate drive sink current for post-discharge period. Adjustment rate configured with the KP_PST control register.
tPST_DCHR Gate drive source current post-charge period duration.
IFW_CHR Freewheeling charge current. Configured with the FW_MAX control register.
IFW_DCHR Freewheeling discharge current. Configured with the FW_MAX control register.
STC tRISE Time duration for VSHx to cross from VSHx_L to VSHx_H threshold. Configured with the T_RISE_FALL control register.
tFALL Time duration for VSHx to cross from VSHx_H to VSHx_L threshold. Configured with the T_RISE_FALL control register.