SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.6 Sense Output (IPROPI)

The device features an output for current sensing, voltage node monitoring, and die temperature on the IPROPI pin. This information can be used for status or regulation of loads (on OUTx), check die temperature, or to provide local motor voltage. These integrated features eliminate the need for multiple external sense resistors or sense circuitry, reducing system size, cost and complexity.

The load currents are sensed by using a shunt-less high-side current mirror topology. The output is a fixed ratio of the instantaneous current of the enabled driver (OUTx). The signal at the output IPROPI is blanked for tIPROPI_BLKafter switching on the driver to allow time for the circuitry to settle. Bit IPROPI_SEL defines which of the outputs is multiplexed to the IPROPI pin, the control values shown in the table below:

Table 7-45 IPROPI_SEL Options
IPROPI_SEL Output
00000b No output
00001b OUT1 Current Sense
00010b OUT2 Current Sense
00011b OUT3 Current Sense
00100b OUT4 Current Sense
00101b OUT5 Current Sense
00110b OUT6 Current Sense
00111b OUT7 Current Sense
01000b OUT8 Current Sense
01001b OUT9 Current Sense
01010b OUT10 Current Sense
01011b OUT11 Current Sense
01100b OUT12 Current Sense
01101b RSVD
01110b RSVD
01111b RSVD
10000b PVDD Output voltage
10001b Thermal Cluster 1
10010 Thermal Cluster 2
10011 Thermal Cluster 3
10100 Thermal Cluster 4

Since the IPROPI pin is a multi-purpose pin which can also be used as second PWM pin control input option for half-bridges, the IPROPI/PWM2 pin mode is controlled with bit IPROPI_MODE in register IC_CTRL.

The diagram below shows the simple block diagram for the selectable IPROPI output:

DRV8000-Q1 IPROPI Output Circuit Figure 7-34 IPROPI Output Circuit

For current output, the IPROPI output analog current is scaled by AIPROPI as follows:

Equation 3. IIPROPI = IOUTX / AIPROPI

For voltage output of PVDD, the voltage is scaled down by a factor of 32 from a range of 4.5V to 40V. The PVDD voltage output is as follows:

VIPROPI = VPVDD / 32

For example:

  • IPROPI_SEL is selected for PVDD
  • PVDD is 13.5V
  • VIPROPI = 0.422V

The IPROPI output can also provide analog voltage representation of any single of the four thermal cluster temperature. This is intended for use in testing and evaluation, but not during device run-time.

For voltage conversion of thermal cluster temperature output reading, the voltage is scaled according to the temperature range -40°C to 185°C and output voltage range of 0V to 3V. The voltage read out :

VIPROPI = A + B*Cluster Temperature

where A is offset roughly equal to 980mV, and B is slope of 2mV/°C.

When the cluster temperature is -40°C, the IPROPI output voltage will be 980mV. At 185°C the IPROPI voltage will be 1.35V.

The IPROPI pin must be connected to an external resistor (RIPROPI) to ground in order to generate proportional voltage VIPROPI. This allows for the load current to be measured as a voltage-drop across the RIPROPI resistor in the application so that the full range of the controller ADC is utilized.

When the output is switched off, the current monitor output is in high impedance mode. The IPROPI output also has an optional sample and hold circuit that can be enabled with bit IPROPI_SH_EN in register HB_OUT_CNFG1.