JAJSUL1A May 2024 – July 2024 DRV8161 , DRV8162
ADVANCE INFORMATION
When nDRVOFF is driven low, the gate driver goes into shutdown, overriding signals on inputs pins INH/IN and INL/EN. nDRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver output. This pin provides a mechanism for externally monitored faults to disable gate driver by directly bypassing an external controller or the internal control logic. When DRV816x detect the nDRVOFF pin is driven low, the device disables the gate driver and puts it into pulldown mode. The gate driver shutdown sequence proceeds as shown in Figure 7-17. When the gate driver initiates the shutdown sequence, the active driver pulldown is applied at IDRVN_SD current for the tDRVN_SD time.