JAJSUL1A May   2024  – July 2024 DRV8161 , DRV8162

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode (preview only)
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

 VGVDD = 12 V, VVDRAIN = 48 V, CSAREF = 5V, TJ = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (GVDD, BST)
IVDRAIN_UNPWR VDRAIN leakage current under GVDD unpowered  GVDD = 0V, VDRAIN = 48V, VBST-SH = 0V

 3.5 5 µA
IGVDD GVDD active mode current INH = INL = Switching @ 20kHz; VBST = VGVDD; No FETs connected, DT/MODE Pin open.  VDS_LVL = 2V 2 mA
tWAKE Turnon time GVDD = 0V to 12V
VGVDD = VGVDD_UV to active mode (outputs ready : nFAULT = High)		 0.4 ms
ILBS_TCPON Bootstrap pin leakage current during high-side pull-up INH = high; TCP_ON 30 µA
LOGIC-LEVEL INPUTS (INH, INL, nDRVOFF)
VIL Input logic low voltage INL, INH, nDRVOFF 0.8 V
VIH Input logic high voltage INL, INH, nDRVOFF 2.2 V
RPU Input pullup resistance nDRVOFF to internal regulator, no external connection 250 kΩ
RPD Input pulldown resistance INH, INL to GND 250 kΩ
tnDRVOFF_DEG nDRVOFF input deglitch time nDRVOFF falling and rising

 2.1 µs
tnDRVOFF_DIAG nDRVOFF diagnostic pulse valid input time DRV8162 and DRV8162L only 0.5 µs
OPEN-DRAIN OUTPUT (nFAULT)
VOL Output logic low voltage IOD = 5 mA, GVDD > 4V 0.4 V
BOOTSTRAP DIODE (BST)
VBOOTD Bootstrap diode forward voltage IBOOT = 10 mA 0.8 V
IBOOT = 100 mA 1.3
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 4.8 Ω
CHARGE PUMP (BST)
VTCP Trickle charge pump output voltage
VBST-SH , INH = High, VSH = VVDRAIN = 20V, VBST > VGVDD, External load ITRICKLE = 2uA, TJ = 25℃		 8.5 V

VBST-SH , INH = High, VSH = VVDRAIN = 20V, VBST > VGVDD, External load ITRICKLE = 2uA, TJ = 150℃		 4.9
GATE DRIVERS (GH, GL, SH, SL)
IDRIVEP0 Peak source gate current VBST-VSH = VGVDD = 12V 16 mA
IDRIVEP1 VBST-VSH = VGVDD = 12V 32
IDRIVEP2 VBST-VSH = VGVDD = 12V 64
IDRIVEP3 VBST-VSH = VGVDD = 12V 96
IDRIVEP4 VBST-VSH = VGVDD = 12V 128
IDRIVEP5 VBST-VSH = VGVDD = 12V 160
IDRIVEP6 VBST-VSH = VGVDD = 12V 192
IDRIVEP7 VBST-VSH = VGVDD = 12V 224
IDRIVEP8 VBST-VSH = VGVDD = 12V 256
IDRIVEP9 VBST-VSH = VGVDD = 12V 288
IDRIVEP10 VBST-VSH = VGVDD = 12V 320
IDRIVEP11 VBST-VSH = VGVDD = 12V 384
IDRIVEP12 VBST-VSH = VGVDD = 12V 448
IDRIVEP13 VBST-VSH = VGVDD = 12V 512
IDRIVEP14 VBST-VSH = VGVDD = 12V 768
IDRIVEP15 VBST-VSH = VGVDD = 12V 1024
IDRIVEN0
Peak sink gate current

 VBST-VSH = VGVDD = 12V 32 mA
IDRIVEN1 VBST-VSH = VGVDD = 12V 64
IDRIVEN2 VBST-VSH = VGVDD = 12V 128
IDRIVEN3 VBST-VSH = VGVDD = 12V 192
IDRIVEN4 VBST-VSH = VGVDD = 12V 256
IDRIVEN5 VBST-VSH = VGVDD = 12V 320
IDRIVEN6 VBST-VSH = VGVDD = 12V 384
IDRIVEN7 VBST-VSH = VGVDD = 12V 448
IDRIVEN8 VBST-VSH = VGVDD = 12V 512
IDRIVEN9 VBST-VSH = VGVDD = 12V 576
IDRIVEN10 VBST-VSH = VGVDD = 12V 640
IDRIVEN11 VBST-VSH = VGVDD = 12V 768
IDRIVEN12 VBST-VSH = VGVDD = 12V 896
IDRIVEN13 VBST-VSH = VGVDD = 12V 1024
IDRIVEN14 VBST-VSH = VGVDD = 12V 1536
IDRIVEN15 VBST-VSH = VGVDD = 12V 2048
RPD_LS Low-side passive pull down GL to SL, VGL - VSL = 2V 85 kΩ
RPDSA_HS High-side semi active pull down VGVDD < VGVDD_UV  
GH to SH, VGH - VSH = 2V
 4 kΩ
IPUHOLD_HS High-side pull-up hold current 512 mA
IPDHOLD_HS High-side pull-down hold current 2048 mA
IPDSTRONG_LS Low-side pull-down strong current 2048 mA
IPDSTRONG_HS High-side pull-down strong current 2048 mA
IDRVIVENSD_LS Low-side peak sink gate shutdown current IDRIVENx is set to  IDRIVEN13 (1024mA  Typ) or smaller settings 32 mA
IDRVIVENSD_LS Low-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA  Typ) or IDRIVEN15 (2048mA  Typ) 64 mA
IDRIVENSD_HS High-side peak sink gate shutdown current IDRIVENx is set to  IDRIVEN13 (1024mA  Typ) or smaller settings 32 mA
IDRIVENSD_HS High-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA  Typ) or IDRIVEN15 (2048mA  Typ) 64 mA
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay INL to GL rising, no load on GL 50 ns
tPDF_LS Low-side falling propagation delay INL to GL falling, no load on GL 50 ns
tPDR_HS High-side rising propagation delay INH to GH rising, no load on GH 50 ns
tPDF_HS High-side falling propagation delay INH to GH falling, no load on GH 50 ns
tPD_MATCH Matching propagation delay of low-side gate driver GL turning ON to GL turning OFF, From VGL-SL = 1V to VGL-SL = VGVDD - 1V;, no load on GL ±4 ns
tPD_MATCH Matching propagation delay of high-side gate driver GH turning ON to GH turning OFF, From VGH-SH = 1V to VGH-SH = VBST-SH - 1V;  no load on GH ±4 ns
tPD_MATCH_PH Matching propagation delay per phase from GL off to GH on Deadtime disabled. GL turning OFF to GH turning ON, From VGL-SL = VGVDD - 1V to VGH-SH = 1V ±4 ns
tPD_MATCH_PH Matching propagation delay per phase from GH off to GL on Deadtime disabled. GH turning OFF to GL turning ON, From VGH-SH = VBST-SH - 1V to VGL-SL = 1V ±4 ns
tDEAD Gate drive dead time RDT = 470 Ω   2-pin PWM mode; IDRIVEN15 20
ns
RDT = 1.3 KΩ   2-pin PWM mode; IDRIVEN15 100
RDT = 3.3 KΩ   2-pin PWM mode; IDRIVEN15 370
tMINDEAD_VGS Minimum gate drive dead time (shortest available)  of VGS monitor mode VGS monitor dead time insertion; tDEAD_CFG < 130ns; HS falling to LS rising, LS falling to HS rising 280 ns
CURRENT SHUNT AMPLIFIERS (SN, SO, SP, CSAREF)
ACSA Sense amplifier gain CSAGAIN = Tied to GND  (LEVEL0) 5 V/V
CSAGAIN = 10kΩ typ tied to GND (LEVEL1) 10 V/V
CSAGAIN = 30kΩ typ tied to GND (LEVEL2) 20 V/V
CSAGAIN = open;  (LEVEL3) 40 V/V
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CSO = 500pF 0.6 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CSO = 500pF 0.8 µs
BW Bandwidth ACSA = 5 V/V, CLOAD = 60-pF, small signal -3 dB 5 MHz
VSWING Output voltage range VCSAREF = 3 to 5.5 V

 0.25 VCSAREF - 0.25 V
VCOM Common-mode input range
-0.225 0.225 V
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 10, 20, 40 V/V
 -1.3 1.3 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 5 V/V
 		 -2.6 2.6 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND, ; –40℃ ≤ TJ ≤ 150℃ 
 8 µV/℃
IBIAS Input bias current VSP = VSN = GND, VCSAREF = 3V to 5.5V 100 µA
IBIAS_OFF Input bias current offset ISP – ISN -1 1 µA
CMRR Common-mode rejection ratio DC 80 dB
20 kHz 60 dB
ICSA_SUP Supply current for CSA CSAREF, VCSAREF = 3.V to 5.5V 1.5 mA
TCMREC Common mode recovery time 2 us
PROTECTION CIRCUITS
VGVDD_UV GVDD undervoltage threshold VGVDD rising
 7.4 V
VGVDD falling 6.7 V
VGVDD_UV GVDD undervoltage threshold VGVDD rising, DRV8162L
 4.8 V
VGVDD falling, DRV8162L 4.7
VBST_UV Bootstrap undervoltage threshold VBST - VSH; VBST rising, GVDD = 12V 7.43 V
VBST - VSH; VBST falling, GVDD = 12V  7.25
VBST - VSH; VBST rising, GVDD = 5V, DRV8162L
 4.08
VBST - VSH; VBST falling, GVDD = 5V, DRV8162L
 3.94
VDS_LVL0-0 VDS overcurrent protection threshold level (DC) RVDSLVL = 0.1 KΩ max (LEVEL0) 0.1 V
VDS_LVL1-1 RVDSLVL = 2 KΩ typ  (LEVEL1); one pulse detected on VDSLVL pin 0.15
VDS_LVL1-0 RVDSLVL = 2 KΩ typ (LEVEL1); DC 0.2
VDS_LVL2-1 RVDSLVL = 5.6 KΩ typ  (LEVEL2); one pulse detected on VDSLVL pin 0.3
VDS_LVL2-0 RVDSLVL = 5.6 KΩ typ (LEVEL2) 0.4
VDS_LVL3-1 RVDSLVL = 12 KΩ typ (LEVEL3); one pulse detected on VDSLVL pin 0.5
VDS_LVL3-0 RVDSLVL = 12 KΩ typ (LEVEL3) 0.6
VDS_LVL4-1 RVDSLVL = 26 KΩ typ (LEVEL4); one pulse detected on VDSLVL pin 0.7
VDS_LVL4-0 RVDSLVL = 26 KΩ typ (LEVEL4) 0.8
VDS_LVL5-1 RVDSLVL = 62 KΩ  typ (LEVEL5); one pulse detected on VDSLVL pin 0.9
VDS_LVL5-0 RVDSLVL = 62 KΩ typ (LEVEL5) 1.0
VDS_LVL6-1 RVDSLVL = 130 KΩ  typ (LEVEL6) ; one pulse detected on VDSLVL pin VDSLVL 1.5
VDS_LVL6-0 RVDSLVL = 130 KΩ  typ (LEVEL6); 2.0
tDS_DG VDS protection deglitch time  3 µs
tDS_BLK VDS overcurrent protection blanking time  1 µs
tVDSLVLFIL VDSLVL pin digital input - one pulse filter time for LEVELx-1  4 µs
VIHVDSLVL VDSLVL pin digital input - one pulse high-level detection voltage for LEVELx-1 1 V
TOTSD Thermal shutdown temperature
 		 170 °C