JAJSUL1A May   2024  – July 2024 DRV8162

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode (preview only)
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRV8161 DRV8162 DRV8161 (Advance Information) DGS Package20-pin VSSOPTop ViewFigure 5-1 DRV8161 (Advance Information) DGS Package20-pin VSSOPTop View
DRV8161 DRV8162 DRV8162 (Product Preview) and DRV8162L (Advance Information) DGS Package20-pin VSSOPTop ViewFigure 5-2 DRV8162 (Product Preview) and DRV8162L (Advance Information) DGS Package20-pin VSSOPTop View
Table 5-1 Pin Functions—DRV816x Devices
PIN TYPE DESCRIPTION
NAME NO.
DRV8161
20-pin		 DRV8162, DRV8162L
20-pin
DT/MODE 1 1 I Selects input pin interface logic and gate drive dead time setting. Connect a resistor between DT and GND to adjust dead time between 20 ns to 1000 ns, and select a PWM mode.
INLH/IN 2 2 I Gate driver control input. Gate driver control depends on DT/MODE pin setting.
INL/EN 3 3 I Gate driver control input. Gate driver control depends on DT/MODE pin setting.
NC — 4 N/A No Connect. Leave open.
nDRVOFF — 5 I Gate driver shutdown control. Pulling nDRVOFF low turns off high-side and low-side external MOSFETs by putting the gate drivers into the pull-down state.
nFAULT/nDRVOFF 4 — I/OD Shared fault indicator pin and gate driver shutdown pin. Connect this pin to an external pull-up resistor to the controller supply or a controller output pin. This pin is pulled logic low during a fault condition. To active gate drive shutdown, pull the pin low by external logic.
nFAULT — 6 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to controller I/O supply, 3.3V to 5.0V.
VDSLVL 5 7 I VDS monitor threshold setting. This pin is a multilevel input pin set by an external resistor.
CSAREF 6 — PWR Current sense amplifier reference. Connect a capacitor between the CSAREF and GND pins.
SO 7 — O Current sense amplifier output.
CSAGAIN 8 — I Gain settings for current sense amplifier. This pin is a multilevel input pin set by an external resistor.
IDRIVE1 9 8 I Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor.
NC 9, 16 No Connect. Leave open.
GVDD 10 10 PWR Gate driver power supply input. Connect a capacitor between the GVDD and GND pins.
IDRIVE2 11 11 I Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor.
GND 12 12 PWR Device ground.
GVDD_LS — 13 PWR Low-side gate driver power supply input (DRV8162 and DRV8162L only). Connect a capacitor between the GVDD_LS and GND pins.
SN 13 — I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SP 14 — I Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SL 15 14 I Low-side source pin. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor and the output for the low-side gate driver sink.
GL 16 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GH 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
SH 18 18 I High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
BST 19 19 O Bootstrap output pin. Connect a capacitor between BST and SH.
VDRAIN 20 20 PWR High-side MOSFET drain sense input for VDS monitor and charge pump reference. Connect to the high-side MOSFET drain.
THERMAL PAD PWR Leave open, or tied to GND

PWR = power, I = input, O = output, NC = no connection, OD = open-drain output