JAJSUL1A May   2024  – July 2024 DRV8161 , DRV8162

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode (preview only)
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Absolute Maximum Ratings

Over recommended operating conditions (unless otherwise noted)(1)
MIN MAX UNIT
Gate driver regulator pin voltage GVDD, GVDD_LS -0.3 20 V
High-side drain pin voltage VDRAIN, TJ = 25℃
 -0.3 102 V
Bootstrap pin voltage BST, TJ = 25℃
 -0.3 115 V
Bootstrap pin voltage BST with respect to SH -0.3 20 V
Logic pin voltage  nFAULT -0.3 20 V
INH(IN), INL(EN), nDRVOFF, VDSLVL -0.3 20
DT/MODE, IDRIVE1, IDRIVE2, CSAGAIN -0.3 6
High-side gate drive pin voltage GH, TJ = 25℃
GVDD >= 11V		 -5 115 V
High-side gate drive pin voltage GH with respect to SH -0.3 20 V
High-side source pin voltage  SH, DC -5 105 V
Transient high-side source pin negative voltage   SH, 1 µs -20 V
High-side source pin slew rate SH , VBST-SH >3.5V 20 V/ns
Low-side gate drive pin voltage GL with respect to SL -0.3 20 V
Low-side source sense pin voltage SL -5 VGVDD+0.3 V
Transient low-side source sense pin negative voltage SL, 1 µs -16 V
Current sense amplifier reference input pin voltage CSAREF -0.3 5.5 V
Shunt amplifier input pin voltage SN, SP -1 1 V
Transient 500-ns shunt amplifier input pin voltage SN, SP, 500ns -16 20 V
Shunt amplifier output pin voltage SO -0.3 VCSAREF + 0.3 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime