SLDS272 September   2024 DRV81620-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active mode
          5. 7.3.2.1.5 Limp Home mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 3 V to 5.5 V, VM = 4 V to 40 V, TJ = -40 °C to +150 °C (unless otherwise noted)

Typical values: VDD = 5 V, VM = 13.5 V, TJ = 25 °C

PARAMETERTEST CONDITIONSMINTYPMAXUNIT

POWER SUPPLY (VM, VDD)

VM_OP

VM minimum operating voltage

ENx = 1b, from UVRVM = 1b to VDS ≤ 1 V, RL = 50 Ω

4

V

VDD_OP

VDD operating voltage

fSCLK = 5 MHz

3

5.5

V

VMDIFF

Voltage difference between VM and VDD

210

mV

IVM_SLEEP

Analog supply current in sleep mode

nSLEEP, IN0, IN1 floating, VM = 28 V, nSCS = VDDTJ ≤ 85 °C

3.2

4

μA

TJ = 150 °C

5.2

20

IVDD_SLEEP

Logic supply current in sleep modenSLEEP, IN0, IN1 floating, nSCS = VDDTJ ≤ 85 °C

0.5

2.5

μA
TJ = 150 °C

10

ISLEEP

Overall current consumption in Sleep modenSLEEP, IN0, IN1 floating, VM = 28 V, nSCS = VDDTJ ≤ 85 °C

6.5

μA
TJ = 150 °C

30

μA

IVM_IDLE

Analog supply current in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, IOLx = 0b, nSCS = VDD

2.2

mA

COR mode, VM ≤ VDD - 1 V

0.4

mA

IVDD_IDLELogic supply current in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, nSCS = VDD

0.4

mA

COR mode, VM ≤ VDD - 1 V

2.2

IIDLEOverall current consumption in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, IOLx = 0b, nSCS = VDD

2.6

mA

IVM_ACT_OFF

Analog supply current in Active mode - channels OFFnSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 0b, IOLx = 0b, nSCS = VDD

7.7

mA

COR mode, VM ≤ VDD - 1 V

3

5

mA

IVM_ACT_ONAnalog supply current in Active mode - channels ONnSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 1b, IOLx = 0b, nSCS = VDDEN_OLON = 0100b

8.7

mA

COR mode, VM ≤ VDD - 1 V

2.3

5

mA

IVDD_ACT_OFFLogic supply current in Active mode - channels OFFnSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 0b, nSCS = VDD

0.3

mA

COR mode, VM ≤ VDD - 1 V

2.7

mA

IVDD_ACT_ONLogic supply current in Active mode - channels ONnSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 1b, nSCS = VDD

0.3

mA

COR mode, IOLx = 0b, EN_OLON = 0100b, VM ≤ VDD - 1 V

3.5

mA

IACT_OFFOverall current consumption in Active mode - channels OFF

nSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 0b, IOLx = 0b, nSCS = VDD

8

mA

IACT_ONOverall current consumption in Active mode - channels ONnSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, ENx = 1b, IOLx = 0b, EN_OLON = 0100b, nSCS = VDD

9

mA

tS2I

Sleep to Idle delay

From nSLEEP pin to TER + INST register = 8680H

240

300

μs

tI2S

Idle to Sleep delay

From nSLEEP pin to standard diagnosis = 0000H, external pull-down from SDO to GND

100

150

μs

tI2A

Idle to Active delay

From INx or nSCS pins to MODE = 10b

100

150

μs

tA2I

Active to Idle delay

From INx or nSCS pins to MODE = 11b

100

150

μs

tS2LH

Sleep to Limp Home delay

From INx pins to VDS = 10% VM

350 + tON

450 + tONμs

tLH2S

Limp Home to Sleep delay

From INx pins to standard diagnosis = 0000H, external pull-down from SDO to GND200 + tOFF250 + tOFF

μs

tLH2A

Limp Home to Active delay

From nSLEEP pin to MODE = 10b

50

100

μs

tA2LH

Active to Limp Home delay

From nSLEEP pin to TER + INST register = 8683H (IN0 = IN1 = logic high) or 8682H (IN1 = logic high, IN0 = logic low) or 8681H (IN1 = logic low, IN0 = logic high)

52

100

μs

tA2S

Active to Sleep delay

From nSLEEP pin to standard diagnosis = 0000H, external pull-down from SDO to GND

50

100

μs

CONTROL AND SPI INPUTS (nSLEEP, IN0, IN1, nSCS, SCLK, SDI)

VIL

Input logic low voltage

0

0.8

V

VIH

Input logic high voltage (nSLEEP, IN0, IN1)

2

5.5

V

VIH_SPIInput logic high voltage (nSCS, SCLK, SDI)

2

VDD

V

IIL

Input logic low current (all pins except nSCS)

VI = 0.8 V

9

12

16

μA

IIH

Input logic high current (all pins except nSCS)

VI = 2 V

20

30

40

μA
IIL_nSCSnSCS input logic low currentVnSCS = 0.8 V, VDD = 5 V

25

60

75

μA

IIH_nSCS

nSCS input logic high currentVnSCS = 2 V, VDD = 5 V

20

40

65

μA

PUSH-PULL OUTPUT (SDO)

VSDO_L

Output logic low voltage

ISDO = -1.5 mA

0

0.4

V

VSDO_H

Output logic high voltage

ISDO = 1.5 mA

VDD - 0.4

VDD

V

ISDO_OFF

SDO tristate leakage current

VnSCS = VDD, VSDO = 0 V or VDD

-0.5

0.5

μA

POWER STAGE

RDS(ON)

ON resistance

TJ = 25 °C

0.63

0.85

Ω

TJ = 150 °C, IL = IL_EAR = 220 mA

0.95

1.3

IL_NOM

Nominal load current (all channels active)

TA = 85 °C, TJ ≤ 150 °C

330

500

mA

TA = 105 °C, TJ ≤ 150 °C

260

500

mA

IL_NOMNominal load current (half of the channels active)TA = 85 °C, TJ ≤ 150 °C

470

500

mA

IL_EAR

Load current for maximum energy dissipation - repetitive (all channels active)

TA = 85 °C, TJ ≤ 150 °C

220

mA

-IL_REV

Inverse current capability per channel (in High-Side operation)IL_EAR

mA

EAR

Maximum energy dissipation repetitive pulses- 2*IL_EAR (two channels in parallel)TJ(0) = 85 °C, IL(0) = 2*IL_EAR, 2*106 cycles, PAR = 1b for affected channels

15

mJ

VDS_OPPower stage voltage drop at low battery for auto-configurable channelsRL = 50 Ω, connected to VM or ground, VM = VM_OP,max, VDx = VM_OP,max

0.2

V

VDS_OPPower stage voltage drop at low battery for low-side channelsRL = 50 Ω, supplied by VM = 4 V, VM = VM_OP,max

0.2

V

VDS_OPPower stage voltage drop at low battery for high-side channelsRL = 50 Ω, VM = VM_OP,max, VM_HS = VM_OP,max

0.2

V

VDS_CLDrain to Source Output clamping voltage for low-side channelsIL = 20 mA,

VM = VOUT_Dx = 36 V

44

46

48

V

VOUT_CL

Source to Ground Output clamping voltage for high-side channels

IL = 20 mA, VM = VOUT_Dx = 7 V

-23

-19

V

IL_OFFOutput leakage current (each low-side channel)VIN = 0 V or floating, VDS = 28 V, ENx = 0b, TJ ≤ 85 °C

0.6

1.5

μA
IL_OFFOutput leakage current (each low-side channel)VIN = 0 V or floating, VDS = 28 V, ENx = 0b, TJ = 150 °C

1

4

μA
IL_OFFOutput leakage current (each auto-configurable or high-side channel)VIN = 0 V or floating, VDS = 28 V, VOUT_S = 1.5 V, ENx = 0b, TJ ≤ 85 °C

0.3

2

μA
IL_OFFOutput leakage current (each auto-configurable or high-side channel)VIN = 0 V or floating, VDS = 28 V, VOUT_S = 1.5 V, ENx = 0b, TJ = 150 °C

0.5

3

μA
tDLY_ONTurn-ON delay (from INx pin or bit to VOUT = 90% VMfor low-side configuration or to VOUT = 10% VM for high-side configuration)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

3

5.5

8

μs
tDLY_OFFTurn-OFF delay (from INx pin or bit to VOUT = 10% VMfor low-side configuration or to VOUT = 90% VM for high-side configuration)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

5

8.5

12

μs
tONTurn-ON time (from INx pin or bit to VOUT = 10% VMfor low-side configuration or to VOUT = 90% VM for high-side configuration)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

10

15

20

μs
tOFFTurn-OFF time (from INx pin or bit to VOUT = 90% VMfor low-side configuration or to VOUT = 10% VM for high-side configuration)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

12

18

24

μs
tON - tOFFTurn-ON/OFF matchingRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

-10

0

10

μs
SRONTurn-ON slew rate, VDS = 70% to 30% VM for low-side configuration or VDS = 30% to 70% VM for high-side configurationRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode, SR = 0b

1

1.45

1.9

V/μs
RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode, SR = 1b

2

2.8

3.6

V/μs
SROFFTurn-OFF slew rate, VDS = 30% to 70% VM for low-side configuration or VDS = 70% to 30% VM for high-side configurationRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode, SR = 0b

0.9

1.4

1.9

V/μs
RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode, SR = 1b

1.8

2.6

3.4

V/μs

tINRUSH

Bulb inrush mode restart time

Active Mode

40

μs

tBIM

Bulb inrush mode reset time

Active Mode

40

ms

fINT

Internal reference frequency

FPWM = 1000b

80

102

125

kHz

fINT_VARInternal reference frequency

variation

-15

15

%

tSYNCInternal reference frequency synchronization time

FPWM = 1000b

5

10

μs

PROTECTION

VM_UVLO_FVM undervoltage shutdown (falling)ENx = ON, from VDS ≤ 1 V to UVRVM = 1b, RL = 50 Ω

2.6

2.73

2.86

V

VM_UVLO_RVM undervoltage shutdown (rising)

2.7

2.85

3

V

VDD_UVLOVDD undervoltage shutdownVSDI = VSCLK = VnSCS = 0 V, SDO from low to Hi-Z

2.55

2.7

2.85

V

VDD_HYS

VDD undervoltage shutdown hysteresis

100

120

140

mV

IL_OCP0

Overcurrent protection threshold, OCP = 0b

TJ = -40 °C

1.2

1.55

1.9

A

TJ = 25 °C

1.2

1.5

1.8

A

TJ = 150 °C

1.2

1.45

1.7

A

IL_OCP1Overcurrent protection threshold, OCP = 0bTJ = -40 °C

0.6

0.85

1.1

A

TJ = 25 °C

0.6

0.8

1

A

TJ = 150 °C

0.6

0.75

0.9

A

IL_OCP0Overcurrent protection threshold, OCP = 1bTJ = -40 °C

1.9

2.3

2.7

A
TJ = 25 °C

1.9

2.2

2.5

A
TJ = 150 °C

1.8

2.05

2.3

A
IL_OCP1Overcurrent protection threshold, OCP = 1bTJ = -40 °C

0.9

1.2

1.5

A
TJ = 25 °C

0.9

1.15

1.4

A
TJ = 150 °C

0.9

1.1

1.3

A
tOCPINOvercurrent threshold switch delay time

110

170

260

μs
tOFF_OCPOvercurrent shut-down delay time

BIMx = PARx = 0b

4

7

11

μs

TOTW

Overtemperature warning

120

140

160

°C

THYS_OTW

Overtemperature warning

hysteresis

12

°C

TTSD

Thermal shut-down temperature

150

175

200

°C
VM_AZ

Over voltage protection

IVM = 10 mA, Sleep mode

45

47

49

V

VDS_REVDrain Source diode during reverse polarity (low-side switch configuration)IL = -10 mA, Sleep mode, TJ = 25 °C

750

mV

VDS_REVDrain Source diode during reverse polarity (low-side switch configuration)IL = -10 mA, Sleep mode, TJ = 150 °C

560

mV

RDS_REV

On-State Resistance during Reverse Polarity (high-Side switch configuration)

VM = -VM_REV, IL = IL_EAR

TJ = 25 °C

0.55

Ω

TJ = 150 °C

0.9

Ω

tRETRY0_LHRestart time in Limp Home mode

7

10

13

ms

tRETRY1_LHRestart time in Limp Home mode

14

20

26

ms

tRETRY2_LHRestart time in Limp Home mode

28

40

52

ms

tRETRY3_LHRestart time in Limp Home mode

56

80

104

ms

tOSMOutput Status Monitor comparator settling time

20

μs
VOSMOutput Status Monitor threshold voltage

3

3.3

3.6

V

IOLOutput diagnosis currentVDS = 3.3 V (for low-side configuration), VOUT_S = 3.3 V (for high-side configuration)

60

80

100

μA
ROLOpen Load equivalent resistance

30

220

kΩ

tONMAX

Open Load at ON Diagnosis waiting time before mux activation

OLMAX = 0b

40

58

76

μs

OLMAX = 1b

56

80

104

μs

tOLONSET

Open Load at ON Diagnosis settling time

20

40

μs

tOLONSW

Open Load at ON Diagnosis channel switching time

10

20

μs

IL_OL

Open Load detection threshold current

1

6

10

mA