JAJSU39 April   2024 DRV8235

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Motor Voltage and Speed Regulation
        1. 7.3.6.1 Internal Bridge Control
        2. 7.3.6.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.6.2.1 Speed and Voltage Set
          2. 7.3.6.2.2 Speed Scaling Factor
            1. 7.3.6.2.2.1 Target Speed Setting Example
          3. 7.3.6.2.3 Motor Resistance Inverse
          4. 7.3.6.2.4 Motor Resistance Inverse Scale
          5. 7.3.6.2.5 KMC Scaling Factor
          6. 7.3.6.2.6 KMC
          7. 7.3.6.2.7 VSNS_SEL
        3. 7.3.6.3 Soft-Start and Soft-Stop
          1. 7.3.6.3.1 TINRUSH
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 VM Undervoltage Lockout (VM UVLO)
        4. 7.3.7.4 Overvoltage Protection (OVP)
        5. 7.3.7.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
  9. 8 Register Map
    1. 8.1 DRV8235_STATUS Registers
    2. 8.2 DRV8235_CONFIG Registers
    3. 8.3 DRV8235_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Brushed DC Motor
      1. 9.2.1 Design Requirements
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Application Description
          1. 9.2.2.1.1 Stall Detection Timing
          2. 9.2.2.1.2 Hardware Stall Threshold Selection
      3. 9.2.3 Motor Speed and Voltage Regulation Application
        1. 9.2.3.1 Tuning Parameters
          1. 9.2.3.1.1 Resistance Parameters
          2. 9.2.3.1.2 KMC and KMC_SCALE
            1. 9.2.3.1.2.1 Case I
            2. 9.2.3.1.2.2 Case II
              1. 9.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 9.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 9.2.3.1.2.2.1.2 Tuning KMC
              2. 9.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 9.2.3.1.2.2.2.1 Working Example
      4. 9.2.4 Motor Voltage
      5. 9.2.5 Motor Current
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Stall Detection

The DRV8235 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8235 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. Table 7-8 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.

Table 7-8 Settings for INT_VREF
BitDescription
0bVVREF not fixed
1bVVREF fixed internally at 3 V

The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings.

Table 7-9 EN_STALL configuration
EN_STALLDescription
0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.
1bStall detection enabled.

The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in Table 7-8, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.

The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8235 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.

When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.

When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.

The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -

  • Power-up of the DRV8235

  • Recovering from faults

  • After device exits from sleep mode

  • After recovering from stall, as explained in Table 7-10

The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. Table 7-10 summarizes the SMODE bit settings.

Table 7-10 SMODE configuration
SMODEDescription

Recovery from Stall Condition

0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.

1b

Indication only: the OUTx pins remain active and the STALL bit becomes 1b.

A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.

The IMODE bits determine the behavior of current regulation in the motor driver. Table 7-7 summarizes the IMODE pin settings. For more details on current regulation, see Section 7.3.4.2.

The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.

The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature.

GUID-20240229-SS0I-HR7X-PF3G-QRFPFKLGGG5N-low.svg Figure 7-8 Stall Detection with Latched Disable
GUID-20240229-SS0I-LZTB-CH9G-7SWJKQN1JBZX-low.svg Figure 7-9 Stall Detection with STALL indication only
GUID-20240229-SS0I-BF4T-K5DF-FRDSC7TBGR16-low.svg Figure 7-10 Stall Detection with current regulation during inrush
GUID-20240229-SS0I-P8B2-TTGD-3FH92CQM72QM-low.svg Figure 7-11 Stall Detection with current regulation