JAJSU39 April   2024 DRV8235

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Motor Voltage and Speed Regulation
        1. 7.3.6.1 Internal Bridge Control
        2. 7.3.6.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.6.2.1 Speed and Voltage Set
          2. 7.3.6.2.2 Speed Scaling Factor
            1. 7.3.6.2.2.1 Target Speed Setting Example
          3. 7.3.6.2.3 Motor Resistance Inverse
          4. 7.3.6.2.4 Motor Resistance Inverse Scale
          5. 7.3.6.2.5 KMC Scaling Factor
          6. 7.3.6.2.6 KMC
          7. 7.3.6.2.7 VSNS_SEL
        3. 7.3.6.3 Soft-Start and Soft-Stop
          1. 7.3.6.3.1 TINRUSH
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 VM Undervoltage Lockout (VM UVLO)
        4. 7.3.7.4 Overvoltage Protection (OVP)
        5. 7.3.7.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
  9. 8 Register Map
    1. 8.1 DRV8235_STATUS Registers
    2. 8.2 DRV8235_CONFIG Registers
    3. 8.3 DRV8235_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Brushed DC Motor
      1. 9.2.1 Design Requirements
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Application Description
          1. 9.2.2.1.1 Stall Detection Timing
          2. 9.2.2.1.2 Hardware Stall Threshold Selection
      3. 9.2.3 Motor Speed and Voltage Regulation Application
        1. 9.2.3.1 Tuning Parameters
          1. 9.2.3.1.1 Resistance Parameters
          2. 9.2.3.1.2 KMC and KMC_SCALE
            1. 9.2.3.1.2.1 Case I
            2. 9.2.3.1.2.2 Case II
              1. 9.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 9.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 9.2.3.1.2.2.1.2 Tuning KMC
              2. 9.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 9.2.3.1.2.2.2.1 Working Example
      4. 9.2.4 Motor Voltage
      5. 9.2.5 Motor Current
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Bridge Control

The DRV8235 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.

The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below.

Table 7-2 H-Bridge Control Interface
I2C_BCDescription
0bBridge control configured by using the EN/IN1 and PH/IN2 pins.
1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.

The control interface is selected by the PMODE bit. DRV8235 allows users to choose either Phase-Enable mode or PWM mode, as described below.

Table 7-3 PMODE Functions
PMODEControl Mode
0bPH/EN
1bPWM

The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied.

GUID-3328670C-EFDE-4E8D-A2B0-1A796745B24E-low.svgFigure 7-1 H-Bridge Current Paths

The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.

PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below.

Table 7-4 PH/EN Control Mode (PMODE = 0b)

nSLEEP

EnablePhaseOUT1OUT2Description

0

XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z)

1

1

0

LHReverse (Current OUT2 → OUT1)

1

11HLForward (Current OUT1 → OUT2)

1

0XLLBrake; low-side slow decay
Note:

Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b).

Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b).

PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below.

Table 7-5 PWM Control Mode (PMODE = 1b)

nSLEEP

 Input1 Input2 OUT1 OUT2 Description

0

 X X High-Z High-Z Sleep Mode (H-bridge High-Z)

1

 0

0

 High-Z High-Z Coast (H-bridge High-Z)

1

 0 1 L H Reverse (Current OUT2 → OUT1)

1

1

 0 H L Forward (Current OUT1 → OUT2)

1

1

1

L

L

 Brake; low-side slow decay
Note:

Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b).

Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b).

The following timing diagram shows the timing of the inputs and outputs of the motor driver.

GUID-20231024-SS0I-WRPH-4GJK-ZNM3PQSFD1PW-low.svgFigure 7-2 H-Bridge Timing Diagram

The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.

The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).