JAJSQT9A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Bridge Control

The DRV824x-Q1 family of devices provides three separate modes to support different control schemes with the EN/IN1 and PH/IN2 pins. The control mode is selected through the MODE setting. MODE is a 2-level setting based on the MODE pin for the HW variant or S_MODE bits in the CONFIG3 register for the SPI variant as summarized in Table 7-3:

Table 7-3 Mode table
MODE pin S_MODE bits Device Mode Description
RLVL1OF4 2'b00 PH/EN mode full-bridge mode, EN/IN1 is the PWM input, PH/EN2 is the direction input
RLVL2OF4 2'b01 Reserved Reserved.
RLVL3OF4 2'b10 Reseverd Reserved.
RLVL4OF4 2b'11 PWM mode full-bridge mode where EN/IN1 and PH/IN2 control the PWM respectively depending on the direction

In the HW variant, the MODE pin is latched during device initialization following power-up or wake-up from sleep. Update during operation is blocked.

In the SPI variant of the device, the mode setting can be changed anytime the SPI communication is available by writing to the S_MODE bits. This change is immediately reflected.

The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The device input pins can be powered before the VM is applied. By default, the nSLEEP and DRVOFF pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are present. Both the EN/IN1 and PH/IN2 pins also have internal pull down resistors. The sections below show the truth table for each control mode.

The device automatically generates the optimal dead time needed during transitioning between the high-side and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage feedback. No external timing is required. This scheme ensures minimum dead time while guaranteeing no shoot-through current.
Note:
  1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to - Register - Pin control.
  2. For the SPI (P) variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin. Internally, nSLEEP = 1, always. The control table is valid when VDD > VDDPOR level.
(1) Current sourcing out of the device (VM → OUTx → Load)
(4) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time