JAJST19 February   2024 DRV8262-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
      1. 5.4.1 Transient Thermal Impedance & Current Capability
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Feature Description
    4. 6.4  Device Operational Modes
      1. 6.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 6.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 6.5  Current Sensing and Regulation
      1. 6.5.1 Current Sensing and Feedback
      2. 6.5.2 Current Regulation
        1. 6.5.2.1 Mixed Decay
        2. 6.5.2.2 Smart tune Dynamic Decay
      3. 6.5.3 Current Sensing with External Resistor
    6. 6.6  Charge Pump
    7. 6.7  Linear Voltage Regulator
    8. 6.8  VCC Voltage Supply
    9. 6.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 6.10 Protection Circuits
      1. 6.10.1 VM Undervoltage Lockout (UVLO)
      2. 6.10.2 VCP Undervoltage Lockout (CPUV)
      3. 6.10.3 Logic Supply Power on Reset (POR)
      4. 6.10.4 Overcurrent Protection (OCP)
      5. 6.10.5 Thermal Shutdown (OTSD)
      6. 6.10.6 nFAULT Output
      7. 6.10.7 Fault Condition Summary
    11. 6.11 Device Functional Modes
      1. 6.11.1 Sleep Mode
      2. 6.11.2 Operating Mode
      3. 6.11.3 nSLEEP Reset Pulse
      4. 6.11.4 Functional Modes Summary
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Brushed-DC Motors
        1. 7.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 7.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 7.1.1.3 Power Loss Calculations - Single H-bridge
        4. 7.1.1.4 Junction Temperature Estimation
        5. 7.1.1.5 Application Performance Plots
      2. 7.1.2 Driving Stepper Motors
        1. 7.1.2.1 Stepper Driver Typical Application
        2. 7.1.2.2 Power Loss Calculations
        3. 7.1.2.3 Junction Temperature Estimation
      3. 7.1.3 Driving Thermoelectric Coolers (TEC)
  9. 8 Package Thermal Considerations
    1. 8.1 DDW Package
      1. 8.1.1 Thermal Performance
        1. 8.1.1.1 Steady-State Thermal Performance
        2. 8.1.1.2 Transient Thermal Performance
    2. 8.2 PCB Material Recommendation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supplies
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Typical values are at TA = 25°C. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, DVDD)
IVMVM operating supply currentnSLEEP = 1, No load, VCC = External 5V

5

8

mA
nSLEEP = 1, No motor load, VCC = DVDD

8.5

13

IVMQVM sleep mode supply currentnSLEEP = 03

8

μA
tSLEEPSleep timenSLEEP = 0 to sleep-mode120μs
tRESETnSLEEP reset pulsenSLEEP low to clear fault2040μs
tWAKEWake-up timenSLEEP = 1 to output transition0.751ms
tONTurn-on timeVM > UVLO to output transition0.81.3ms
VDVDDInternal regulator voltageNo external load, 6 V < VVM < 60 V4.7555.25V
No external load, VVM = 4.5 V

4.3

4.45

V

CHARGE PUMP (VCP, CPH, CPL)
VVCPVCP operating voltage6 V < VVM < 60 VVVM + 5V
f(VCP)Charge pump switching frequencyVVM > UVLO; nSLEEP = 1360kHz
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, OCPM, MODE1, MODE2, nSLEEP)
VILInput logic-low voltage00.6V
VIHInput logic-high voltage1.55.5V
VHYSInput logic hysteresis100mV
VHYS

_nSLEEP

nSLEEP logic hysteresis

300

mV

IILInput logic-low current (except MODE2)VIN = 0 V–11μA
IIHInput logic-high current (except MODE2)VIN = 5 V50μA
RPUMODE2 internal pull-up resistor

220

kΩ

tPDH1

INx high to OUTx high propagation delay

600

ns

tPDL1

INx low to OUTx low propagation delay

600

ns

TRI-LEVEL INPUTS (DECAY)
VI1Input logic-low voltageTied to GND

0

0.6

V

VI2Input Hi-Z voltageHi-Z (>500kΩ to GND)

1.8

2

2.2

V

VI3Input logic-high voltageTied to DVDD

2.7

5.5

V

IOOutput pull-up current

10.5

μA
QUAD-LEVEL INPUTS (TOFF)
VI1Input logic-low voltageTied to GND00.6V
VI2330kΩ ± 5% to GND11.251.4V
VI3Input Hi-Z voltageHi-Z (>500kΩ to GND)1.822.2V
VI4Input logic-high voltageTied to DVDD2.75.5V
IOOutput pull-up current10.5μA
CONTROL OUTPUTS (nFAULT)
VOLOutput logic-low voltageIO = 5 mA0.3V
IOHOutput logic-high leakage–11μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ONH_DUAL)Dual H-bridge, High-side FET on resistance

TJ = 25 °C, IO = -5 A

50

60

mΩ
TJ = 125 °C, IO = -5 A

75

94

mΩ
TJ = 150 °C, IO = -5 A

85

107mΩ
RDS(ONL_DUAL)Dual H-bridge, Low-side FET on resistanceTJ = 25 °C, IO = 5 A

50

60

mΩ
TJ = 125 °C, IO = 5 A

72

90

mΩ
TJ = 150 °C, IO = 5 A

80

100mΩ
RDS(ONH_SINGLE)Single H-bridge, High-side FET on resistanceTJ = 25 °C, IO = -5 A

25

30mΩ
TJ = 125 °C, IO = -5 A38

47

mΩ
TJ = 150 °C, IO = -5 A

43

54

mΩ
RDS(ONL_SINGLE)Single H-bridge, Low-side FET on resistanceTJ = 25 °C, IO = 5 A

25

30mΩ
TJ = 125 °C, IO = 5 A

36

45

mΩ
TJ = 150 °C, IO = 5 A

40

50

mΩ

ILEAK

Output leakage current to GND

Sleep-mode, H-bridges are Hi-Z, VVM = 60 V

300

μA
tRFOutput rise/fall timeIO = 5 A, between 10% and 90%

110

ns

tD

Output dead time

VM = 24V, IO = 5 A

300

ns

CURRENT SENSE AND REGULATION (IPROPI, VREF)

AIPROPI

Current mirror gain

212

μA/A

AERR

Current mirror scaling error

10% to 20% rated current

-12

12

%

20% to 40% rated current

-7

7

40% to 100% rated current

-4

4

IVREF

VREF Leakage Current

VREF = 3.3 V

30

nA
tOFFPWM off-timeTOFF = 07μs
TOFF = 116
TOFF = Hi-Z24
TOFF = 330 kΩ to GND32

tDEG

Current regulation deglitch time

0.5

μs

tBLK

Current Regulation Blanking time

1.5

μs
PROTECTION CIRCUITS
VUVLOVM UVLO lockoutVM falling4.14.254.35V
VM rising4.24.354.45
VCCUVLOVCC UVLO lockout

VCC falling

2.7

2.8

2.9

V

VCC rising

2.8

2.9

3.05

VUVLO,HYSUndervoltage hysteresisRising to falling threshold100mV
VCPUVCharge pump undervoltageVCP fallingVVM + 2V
IOCPOvercurrent protectionDual H-bridge, Current through any FET

8

A
Single H-bridge, Current through any FET

16

A
tOCPOvercurrent detection delay

2.1

μs

tRETRY

Overcurrent retry time

4.1

ms

TOTSDThermal shutdownDie temperature TJ150165180°C
THYS_OTSDThermal shutdown hysteresisDie temperature TJ20°C
(1)

Guaranteed by design.

GUID-20220609-SS0I-8R10-F7P3-SS4F8QCJ2HVQ-low.svgFigure 5-1 IPROPI Timing Diagram