JAJSN64 January 2022 DRV8316-Q1
PRODUCTION DATA
The SOx pin on the DRV8316-Q1 outputs an analog voltage proportional to current flowing in the low side FETs multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels which can be set by the GAIN pin (in hardware device variant) or the GAIN bits (in SPI device variant).
Figure 8-27 shows the internal architecture of the current sense amplifiers. The current sense is implemented with the sense FET on each low-side FET of the DRV8316-Q1 device. This current information is fed to the interal I/V converter, which generates the CSA output voltage on the SOX pin based on the voltage on VREF pin and the Gain setting. The CSA output voltage can be calculated as :
Figure 8-28 and Figure 8-29 show the detail of the amplifier operational range. In bi-directional operation, the amplifier output for 0-V input is set at VREF / 2. Any change in the differential input results in a corresponding change in the output times the CSA_GAIN factor. The amplifier has a defined linear region in which it can maintain operation.