JAJSSZ1 December   2023 DRV8334

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions 48-Pin DRV8334
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings DRV8334
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information DRV8334
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 SPI Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode with INLx enable control
          3. 7.3.1.1.3 3x PWM Mode with SPI enable control
          4. 7.3.1.1.4 1x PWM Mode
          5. 7.3.1.1.5 SPI Gate Drive Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Bootstrap diode
          2. 7.3.1.2.2 GVDD Charge pump
          3. 7.3.1.2.3 VCP Trickle Charge pump
          4. 7.3.1.2.4 Gate Driver Output
          5. 7.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 7.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 7.3.1.2.7 Propagation Delay
          8. 7.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 Low-Side Current Sense Amplifiers
        1. 7.3.2.1 Unidirectional Current Sense Operation
        2. 7.3.2.2 Bidirectional Current Sense Operation
      3. 7.3.3 Gate Driver Shutdown
        1. 7.3.3.1 DRVOFF Gate Driver Shutdown
        2. 7.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 7.3.4 Gate Driver Protective Circuits
        1. 7.3.4.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.4.2  GVDD Undervoltage Lockout (GVDD_UV)
        3. 7.3.4.3  BST Undervoltage Lockout (BST_UV)
        4. 7.3.4.4  MOSFET VDS Overcurrent Protection (VDS_OCP)
        5. 7.3.4.5  VSENSE Overcurrent Protection (SEN_OCP)
        6. 7.3.4.6  Phase Comparators
        7. 7.3.4.7  Thermal Shutdown (OTSD)
        8. 7.3.4.8  Thermal Warning (OTW)
        9. 7.3.4.9  OTP CRC
        10. 7.3.4.10 SPI Watchdog Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
      2. 7.4.2 Device Power Up Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Format Diagrams
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.1 Pin Functions 48-Pin DRV8334

GUID-20210625-CA0I-TQ55-FQ9M-4CLCS73TB4KG-low.svg Figure 5-1 DRV8334 Package 48-Pin HTQFP With Exposed Thermal Pad Top View
Table 5-1 Pin Functions (48-QFP)
PIN I/O(1) DESCRIPTION
NAME NO.
GLC 1 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
SLC 2 I Low-side source sense input. Connect to the low-side power MOSFET source.
SPA 3 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNA 4 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SPB 5 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNB 6 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SPC 7 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SNC 8 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
DRVOFF 9 I Active high shutdown input to pull-down gate driver outputs GHx and GLx.
AGND 10 PWR Device ground.
INHA 11 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 12 I/O Low-side gate driver control input. This pin controls the output of the low-side gate driver. This pin can be configured to output buffer of phase comparator by SPI register bit PHC_OUTEN.
INHB 13 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLB 14 I/O Low-side gate driver control input. This pin controls the output of the low-side gate driver. This pin can be configured to output buffer of phase comparator by SPI register bit PHC_OUTEN.
INHC 15 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLC 16 I/O Low-side gate driver control input. This pin controls the output of the low-side gate driver. This pin can be configured to output buffer of phase comparator by SPI register bit PHC_OUTEN.
SDO 17 O Serial data output.
SDI 18 I Serial data input.
SCLK 19 I Serial clock input.
nSCS 20 I Serial chip select.
nSLEEP 21 I Gate driver nSLEEP. When this pin is logic low the device goes to a low-power sleep mode.
nFAULT 22 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
VREF 23 PWR External voltage reference for current sense amplifiers.
SOC 24 O Current sense amplifier output.
SOB 25 O Current sense amplifier output.
SOA 26 O Current sense amplifier output.
GND 27 PWR Device ground
CPL 28 PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins.
CPH 29 PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins.
GVDD 30 PWR Gate driver power supply output. Connect a GVDD-rated ceramic between the GVDD and GND pins.
PVDD 31 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a PVDD-rated ceramic between the PVDD and GND pins.
CPTL 32 PWR Trickle charge pump switching node. Connect a charge pump flying capacitor between CPTL and CPTH pins.
CPTH 33 PWR Trickle charge pump switching node. Connect a charge pump flying capacitor between CPTL and CPTH pins.
VCP 34 PWR Trickle charge pump storage capacitor. Connect a ceramic capacitor between VCP and VDRAIN pins.
VDRAIN 35 PWR High-side drain sense and charge pump power supply input.
BSTA 36 O Bootstrap output pin. Connect a bootstrap capacitor between BSTA and SHA
SHA 37 I High-side source sense input. Connect to the high-side power MOSFET source.
GHA 38 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 39 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
SLA 40 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 41 I Low-side source sense input. Connect to the low-side power MOSFET source.
GLB 42 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GHB 43 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
SHB 44 I High-side source sense input. Connect to the high-side power MOSFET source.
BSTB 45 O Bootstrap output pin. Connect a bootstrap capacitor between BSTB and SHB
BSTC 46 O Bootstrap output pin. Connect a bootstrap capacitor between BSTC and SHC
SHC 47 I High-side source sense input. Connect to the high-side power MOSFET source.
GHC 48 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
(1) Signal Types: I = Input, O = Output, I/O = Input or Output., PWR = Power