JAJSSZ1 December   2023 DRV8334

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions 48-Pin DRV8334
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings DRV8334
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information DRV8334
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 SPI Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode with INLx enable control
          3. 7.3.1.1.3 3x PWM Mode with SPI enable control
          4. 7.3.1.1.4 1x PWM Mode
          5. 7.3.1.1.5 SPI Gate Drive Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Bootstrap diode
          2. 7.3.1.2.2 GVDD Charge pump
          3. 7.3.1.2.3 VCP Trickle Charge pump
          4. 7.3.1.2.4 Gate Driver Output
          5. 7.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 7.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 7.3.1.2.7 Propagation Delay
          8. 7.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 Low-Side Current Sense Amplifiers
        1. 7.3.2.1 Unidirectional Current Sense Operation
        2. 7.3.2.2 Bidirectional Current Sense Operation
      3. 7.3.3 Gate Driver Shutdown
        1. 7.3.3.1 DRVOFF Gate Driver Shutdown
        2. 7.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 7.3.4 Gate Driver Protective Circuits
        1. 7.3.4.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.4.2  GVDD Undervoltage Lockout (GVDD_UV)
        3. 7.3.4.3  BST Undervoltage Lockout (BST_UV)
        4. 7.3.4.4  MOSFET VDS Overcurrent Protection (VDS_OCP)
        5. 7.3.4.5  VSENSE Overcurrent Protection (SEN_OCP)
        6. 7.3.4.6  Phase Comparators
        7. 7.3.4.7  Thermal Shutdown (OTSD)
        8. 7.3.4.8  Thermal Warning (OTW)
        9. 7.3.4.9  OTP CRC
        10. 7.3.4.10 SPI Watchdog Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
      2. 7.4.2 Device Power Up Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Format Diagrams
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤  150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (PVDD)
IPVDDQ PVDD sleep mode current VPVDD = 12 V, nSLEEP = 0, TA = 25°C,  IPVDDQ = PVDD + VDRAIN

 



 16 20 µA
IPVDDQ PVDD sleep mode current VPVDD = 24 V, nSLEEP = 0, TA = 25°C,  IPVDDQ = PVDD + VDRAIN
 16 30 µA
IPVDDQ PVDD sleep mode current VPVDD = < 36V, nSLEEP = 0, TJ < 150C, IPVDDQ = PVDD + VDRAIN
 18 50 µA
IPVDD PVDD active mode current VPVDD = 24 V,  nSLEEP = HIGH, INHx = INLX = Low. No FETs connected, IPVDD = PVDD + VDRAIN, VDRAIN = 24 V

 28 38 mA
IPVDD PVDD active mode current VPVDD = 60 V,  nSLEEP = HIGH, INHx = INLX = Low. No FETs connected, IPVDD = PVDD + VDRAIN, VDRAIN = 60 V, VCP_MODE = 00b, 01b, 11b
 50 mA
IPVDD PVDD active mode current VPVDD = 24 V, nSLEEP = HIGH, INHx = INLX = Switching@20kHz, No FETs connected,  IPVDD = PVDD + VDRAIN


 25 40 mA
IPVDD PVDD active mode current VPVDD = 60 V,  nSLEEP = HIGH, INHx = INLX = Switching@20kHz. No FETs connected, IPVDD = PVDD + VDRAIN, VDRAIN = 60 V, VCP_MODE = 00b, 01b, 11b
      		 55 mA
tWAKE Turn-on time nSLEEP = Low to High; nFAULT goes High.

 
 1 5 ms
LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP etc)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 2.1 V
VHYS Input hysteresis 200 330 450 mV
VIL DRVOFF Input logic low voltage DRVOFF

 		 0.65 V
VIH DRVOFF Input logic high voltage DRVOFF 2.1 V
VHYS DRVOFF Input hysteresis DRVOFF 200 400 600 mV
RPD Input pulldown resistance To GND; INHx, INLx, SCLK, SDI 50 100 150 kΩ
RPD Input pulldown resistance nSLEEP, DRVOFF 460 800 1700 kΩ
IIL Input logic low current VI = 0 V; nSCS (internal pull up); VIO = 3.3V 11 33 66 µA
IIL Input logic low current VI = 0 V; nSCS (internal pull up); VIO = 5V 25 50 100 µA
IIH Input logic high current VI = 5 V, INHx/INLx/SDI/SCLK 30 50 70 µA
VIH nSleep Input logic high voltage 2.1 V
VIL nSleep Input logic low voltage 0.8 V
VHYST nSleep Input logic hysteresis 0.1 V
LOGIC-LEVEL OUTPUTS (nFAULT, SDO, PHCx)
VOL Output logic low voltage IDOUT = 1 mA, PHCOMP 0.5 V
VOL Output logic low voltage IDOUT = 1 mA, SDO 0.5 V
VOH Output logic high voltage IDOUT = 1 mA, SDO, 3.3V mode 2.7 3.3 3.6 V
VOH Output logic high voltage IDOUT = 1 mA, PHCOMP, 5V mode; VPVDD  ≥ 4.5V 4.0 5 5.5 V
VOH Output logic high voltage IDOUT = 1 mA, SDO, 5V mode; VPVDD  ≥ 4.5V 4.0 5 5.5 V
VOH Output logic high voltage IDOUT = 1 mA, SDO, 5V mode; 4V ≤VPVDD  < 4.5V 3.6 3.8 4.5 V
IOZ Output logic high current nFAULT : Force nFAULT = 5 V, no fault event, nSLEEP = High
SDO : Force VSDO = 5V, nSCS = High or nSLEEP = Low		 –12 25 µA
IOZ Output logic high current SDO : Force VSDO = 0V, nSCS = High or nSLEEP = Low –12 10 µA
CHARGE PUMP (GVDD, VCP)
VGVDD GVDD Gate driver regulator voltage (LDO mode) 22 V ≤VPVDD ; IGS  ≤50 mA 11.5 13.5 V
18 V ≤VPVDD ≤ 22 V; IGS  ≤ 50 mA 11.5 13.5 V
GVDD Gate driver regulator voltage (Charge pump mode) 7.2 V ≤VPVDD ≤ 18 V; IGS = 50 mA ; IVCP = 5mV 11.5 13.5 V
6.5 V ≤VPVDD ≤ 7.2 V; IGS ≤ 20 mA; IVCP = 3mA 
DIS_GVDD_SS = 1b		 11.5 13.5 V
5 V ≤VPVDD ≤ 6.5 V; IGS ≤ 20 mA; IVCP = 3mA
DIS_GVDD_SS = 1b		 9 13 V
4.5 V ≤VPVDD ≤ 5 V; IGS ≤ 20 mA, IVCP = 3mA;
DIS_GVDD_SS = 1b		 8 10 V
VVCP VCP charge pump voltage (with respect to VDRAIN) VVCP = V(VCP - VDRAIN; 13.5 ≥  GVDD ≥ 11 V; VDRAIN > 4.5V; IVCP  5 mA; 

 9.8 13.5 V
VVCP = V(VCP - VDRAIN) ; 9V ≤ GVDD  < 11V;  VDRAIN > 4.5V; IVCP = 3 mA; 

 8.4 11
VVCP = V(VCP - VDRAIN) ; 8V ≤ GVDD < 9V;  VDRAIN > 4.5V; IVCP = 3 mA; 

 7.4 9
tBST_PRECHG VCP charge pump bootstrap cap pre-charge time VBST-SHX = 5V ;INHx = INLx = Low. Tj = 150C, IVCP = 3mA; CVCP = 1.5uF; CBST = 1.5uF (each phase), CVCP_FLY = 1uF;   VPVDD = 4.5V
 1.7 3 ms
VBST_TCPOFF BST monitor voltage for VCP to stop charging the BST cap (rising voltage) INLx = 0; SHx = 0, VDRAIN; VDRAIN =  PVDD = 12V, 60V; 12.0 13.2 14.6 V
BOOTSTRAP DIODES
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA. 0.85 V
IBOOT = 10 mA.  1 V
IBOOT = 100 mA.  1.6 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA.  5.5 Ω
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGL_L Low-side Low-level output voltage IGLx = 10mA, GLx - SLx; IDRVN = 100100b: IHOLD_SEL = 0b; VGVDD = 12V;  0 0.2 V
VGL_H Low-side High-level output voltage IGLx = 10mA, GVDD - GLx ;  IDRVP = 100100b ; IHOLD_SEL = 0b;  VGVDD = 12V;  0 0.2 V
VGH_L High-side Low-level output voltage IGHx = 10mA, GHx - SHx; IDRVN = 100100b ; IHOLD_SEL = 0b; VGVDD = 12V;  0 0.2 V
VGH_H High-side High-level output voltage IGHx = 10mA, BSTx - GHx; IDRVP = 100100b ; IHOLD_SEL = 0b; VGVDD = 12V;  0 0.2 V
RPDSA_LS Low side semi active pull down resistor GLx to SLx; nSLEEP = Low, VGLx - VSLx = 2V, GVDD (BSTx-SHx) > 2V 2 3 4.3 kΩ
RPDSA_HS High side semi active pull down resistor GHx to SHx; nSLEEP = Low, VGHx - VSHx = 2V, GVDD (BSTx-SHx) > 2V 7 9 12 kΩ
IDRVN Peak sink gate current IDRVN=000000b; VGSx = 5V; BST-SHx = GVDD = 12V 0.75 mA
IDRVN=000001b; VGSx = 5V; BST-SHx = GVDD = 12V 1.1
IDRVN=000010b; VGSx = 5V; BST-SHx = GVDD = 12V 1.5
IDRVN=000011b; VGSx = 5V; BST-SHx = GVDD = 12V 1.9
IDRVN=000100b; VGSx = 5V; BST-SHx = GVDD = 12V 2.3
IDRVN=000101b; VGSx = 5V; BST-SHx = GVDD = 12V 2.8
IDRVN=000110b; VGSx = 5V; BST-SHx = GVDD = 12V 3.4
IDRVN=000111b; VGSx = 5V; BST-SHx = GVDD = 12V 3.9
IDRVN=001000b; VGSx = 5V; BST-SHx = GVDD = 12V 4.4
IDRVN=001001b; VGSx = 5V; BST-SHx = GVDD = 12V 5.3
IDRVN=001010b; VGSx = 5V; BST-SHx = GVDD = 12V 6.3
IDRVN=001011b; VGSx = 5V; BST-SHx = GVDD = 12V 7.2
IDRVN=001100b; VGSx = 5V; BST-SHx = GVDD = 12V 8.1
IDRVN=001101b; VGSx = 5V; BST-SHx = GVDD = 12V 10
IDRVN=001110b; VGSx = 5V; BST-SHx = GVDD = 12V 11
IDRVN=001111b; VGSx = 5V; BST-SHx = GVDD = 12V 13
IDRVN=010000b; VGSx = 5V; BST-SHx = GVDD = 12V 14
IDRVN=010001b; VGSx = 5V; BST-SHx = GVDD = 12V 16
IDRVN=010010b; VGSx = 5V; BST-SHx = GVDD = 12V 18
IDRVN=010011b; VGSx = 5V; BST-SHx = GVDD = 12V 21
IDRVN=010100b; VGSx = 5V; BST-SHx = GVDD = 12V 25
IDRVN=010101b; VGSx = 5V; BST-SHx = GVDD = 12V 29
IDRVN Peak sink gate current IDRVN=010110b; VGSx = 5V; BST-SHx = GVDD = 12V 33 mA
IDRVN=010111b; VGSx = 5V; BST-SHx = GVDD = 12V 38
IDRVN=011000b; VGSx = 5V; BST-SHx = GVDD = 12V 44
IDRVN=011001b; VGSx = 5V; BST-SHx = GVDD = 12V 49
IDRVN=011010b; VGSx = 5V; BST-SHx = GVDD = 12V 68
IDRVN=011011b; VGSx = 5V; BST-SHx = GVDD = 12V 79
IDRVN=011100b; VGSx = 5V; BST-SHx = GVDD = 12V 88
IDRVN=011101b; VGSx = 5V; BST-SHx = GVDD = 12V 106
IDRVN=011110b; VGSx = 5V; BST-SHx = GVDD = 12V 125
IDRVN=011111b; VGSx = 5V; BST-SHx = GVDD = 12V 144
IDRVN=100000b; VGSx = 5V; BST-SHx = GVDD = 12V 163
IDRVN=100001b; VGSx = 5V; BST-SHx = GVDD = 12V 191
IDRVN=100010b; VGSx = 5V; BST-SHx = GVDD = 12V 219
IDRVN=100011b; VGSx = 5V; BST-SHx = GVDD = 12V 247
IDRVP Peak source gate current  IDRV_CFG = 0b; IDRV_RATIO = 00b; IDRVN = 00000b to 100011b ; VGSx = 5V; BST-SHx = GVDD = 12V
 		 1*IDRVN mA
IDRV_CFG = 0b; IDRV_RATIO = 01b; IDRVN = 00000b to 100011b ; VGSx = 5V; BST-SHx = GVDD = 12V
  		 0.75*IDRVN mA
IDRV_CFG = 0b; IDRV_RATIO = 10b; IDRVN = 00000b to 100011b ; VGSx = 5V; BST-SHx = GVDD = 12V
 		 0.5*IDRVN mA
IDRV_CFG = 0b; IDRV_RATIO = 11b; IDRVN = 00000b to 100011b ; VGSx = 5V; BST-SHx = GVDD = 12V
 		 0.25*IDRVN mA
IDRVN_VAR Peak sink gate current variation IDRVN=000000b - 011001b -50 +50 %
IDRVP_VAR Peak source gate current variation IDRVN=011010b - 100011b -50 +80 %
IDRVN Peak sink gate current - switch mode  IDRVN=100100b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. SGD_TMP_EN = 1b 400 600 980 mA
IDRVN=100101b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 480 695 1020 mA
IDRVN=100110b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 560 795 1060 mA
IDRVN=100111b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 640 925 1240 mA
IDRVN=101000b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 760 1090 1440 mA
IDRVN=101001b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 880 1255 1660 mA
IDRVN=101010b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 1020 1455 1920 mA
IDRVN=101011b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 1080 1685 2500 mA
IDRVN=101100b; VGSx (GHx-SHx, GLx-SLx) = 12V;  BST-SHx = GVDD = 12V. 1080 2000 2600 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=100100b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 150 300 450 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=100101b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 177 355 533 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=100110b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 205 410 615 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=100111b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 237 475 713 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=101000b;VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 280 560 840 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=101001b;VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 322 645 968 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=101010b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 375 750 1125 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=101011b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 432 865 1298 mA

IDRVP
 		 Peak source gate current - switch mode   IDRVP=101100b; VGSx (GHx-SHx, GLx-SLx) = 0V; GVDD = 12V 507 1015 1523 mA
IHOLD_PU Gate pull up hold current  IHOLD_SEL = 1b; BST-SHx = GVDD = 12V. 150 250 400 mA
IHOLD_PU Gate pull up hold current  IHOLD_SEL = 0b; BST-SHx = GVDD = 12V. 330 560 900 mA
IHOLD_PD Gate pull down hold current  IHOLD_SEL = 1b; BST-SHx = GVDD = 12V. 140 267 480 mA
IHOLD_PD Gate pull down hold current  IHOLD_SEL = 0b; BST-SHx = GVDD = 12V. 580 1100 1500 mA
ISTRONG Gate pull down strong current  GHx-SHx = 12V (High side) or GLx = 12V (Low Side); BST-SHx = GVDD = 12V. 1000 2000 2800 mA
GATE DRIVER TIMINGS (GHx, GLx)
tPD Input to output propagation delay GHx/GLx falling INHx, INLx to GHx, GLx. IDRVN = IDRVP = 101000b ; After INHx/INLx falling edge to VGS = VGHS/VGLS – 1 V; VGVDD = VBSTx-SHx  ≥ 8V 55 150 ns
tPD Input to output propagation delay GHx/GLx falling INHx, INLx to GHx, GLx. IDRVN = IDRVP = 011101b ; After INHx/INLx falling edge to VGS = VGHS/VGLS – 1 V; VGVDD = VBSTx-SHx  ≥ 8V 75 150 ns
tPD Input to output propagation delay GHx/GLx rising INHx, INLx to GHx, GLx. IDRVN = IDRVP = 101000b; After INHx/INLx rising edge to VGS = 1 V; VGVDD = VBSTx-SHx ≥ 8V 55 150 ns
tPD Input to output propagation delay GHx/GLx rising INHx, INLx to GHx, GLx.IDRVN = IDRVP = 011101b; After INHx/INLx rising edge to VGS = 1 V; VGVDD = VBSTx-SHx ≥ 8V 70 150 ns
tPD_match Matching propagation delay per phase GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx-SHx ≥ 8V –150 10 150 ns
tPD_match Matching propagation delay phase to phase GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx-SHx ≥ 8V –50 10 50 ns
tDRIVE Peak current gate drive time  Typical value.TDRVP (TDRVN) = 0000b - 1111b. Refer to register map TDRNP and TDRVN. 140 3815 ns
tDRIVE_V Peak current gate drive time variation With respect to typical value.TDRVP (TDRVN) = 0000b - 1111b -20 20 %
tDEAD Digital Gate drive dead time  DEADTIME = 000b; 30 70 130 ns
DEADTIME = 001b; 170 214 300 ns
DEADTIME = 010b 230 286 380 ns
DEADTIME = 011b 420 500 640 ns
DEADTIME = 100b 640 750 930 ns
DEADTIME = 101b 880 1000 1280 ns
DEADTIME = 110b 1270 1500 1820 ns
DEADTIME = 111b 1700 2000 2400 ns
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, VREF)
ACSA Sense amplifier gain CSAGAIN = 0000b 5 V/V
CSAGAIN = 0001b; 10 V/V
CSAGAIN = 0010b 12 V/V
CSAGAIN = 0011b 16 V/V
CSAGAIN = 0100b 20 V/V
CSAGAIN = 0101b 23 V/V
CSAGAIN = 0110b 25 V/V
CSAGAIN = 0111b 30 V/V
CSAGAIN = 1000b 40 V/V
EACSA Sense amplifier gain error All CSAGAIN setting 
VGVDD > 7.2V (this GVDD condition is applied to all CSA items)		 -0.5 0.5 %
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, RSO = 160Ω, CSO = 470pF ; VREF = 5V/3V
 0.6 1.35 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD = 470pF 
 0.65 1.35 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 20 V/V, RSO = 160Ω, CSO = 470pF VREF = 5V/3V
 0.7 1.35 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 30 V/V, RSO = 160Ω, CSO = 470pF VREF = 5V 0.7 1.35 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 30 V/V, RSO = 160Ω, CSO = 470pF VREF = 3V 0.7 1.6 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 40 V/V, RSO = 160Ω, CSO = 470pF VREF = 5V 0.7 1.7 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 40 V/V, RSO = 160Ω, CSO = 470pF VREF = 3V 0.7 1.75 µs
UGB Unity Gain Bandwidth CLOAD = 470pF; closed loop, BW @ unity gain 10 MHz
BW Bandwidth closed loop, -3db, no output load 1 MHz
VSWING Output voltage range VVREF = 3 to 5.5 V  0.25 VVREF - 0.25 V
VCOM Common-mode input range VCOM = (VSP + VSN) / 2 -2 2 V
tcom_rec Common-mode transient recovery timing VCOM = -15V to 0V 2.2 µs
VDIFF Differential-mode input range -0.3 0.3 V
VOFF Input offset voltage total VSP = VSN = GND;
Initial offset + Offset drift

 		 –0.65 0.65 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND; temperature drift + aging
 		 –0.2 0.2 mV
IBIAS Input bias current VSP = VSN = GND.  CSA and SENSE_OCP total  20 100 µA
IBIAS_OFF Input bias current offset  ISP – ISN. CSA and SENSE_OCP total  -1 1 µA
IVREF Reference input current VCSAREF = 3.3 V 3 6 9.25 mA
VCSAREF = 5 V 4 7 9.5 mA
CMRR DC Common-mode rejection ratio SN/SP = -2V to 2V 60 90 dB
CMRR Transient Common-mode rejection ratio 20KHz 60 90 dB
PSRR Power-supply rejection ratio 100 dB
Temperature Reporting
SUPPLY VOLTAGE MONITORS
VPVDD_UV PVDD undervoltage lockout threshold VPVDD rising 4.5 4.65 4.8 V
VPVDD falling 4.05 4.2 4.35
VPVDD_UV_HYS PVDD undervoltage lockout hysteresis Rising to falling threshold 400 450 500 mV
tPVDD_UV_DG PVDD undervoltage deglitch time rising and falling edge 8 12 16 µs
VPVDD_UVW PVDD undervoltage warning threshold VPVDD rising; PVDD_UVW_LVL= 0b; 6.0 7 V
VPVDD falling; PVDD_ULW_LVL= 0b; 5.8 6.8 V
VPVDD rising; PVDD_UVW_LVL = 1b; 7.3 8.3 V
VPVDD falling; PVDD_UVW_LVL = 1b; 7.1 8.1 V
VPVDD_UVW_HYS PVDD undervoltage warning hysteresis Rising to falling threshold 140 200 260 mV
tPVDD_UVW_DG PVDD undervoltage warning deglitch time rising and falling edge 8 12 16 µs
VPVDD_OV PVDD overvoltage threshold VPVDD rising, PVDD_OV_LVL = 00b 28 31 V
VPVDD falling, PVDD_OV_LVL = 00b 27 30
VPVDD rising, PVDD_OV_LVL = 01b 33 36
VPVDD falling, PVDD_OV_LVL = 01b 32 35
VPVDD rising, PVDD_OV_LVL = 10b 50 55
VPVDD falling, PVDD_OV_LVL = 10b 47 52
VPVDD_OV_HYS PVDD overvoltage hysteresis Rising to falling threshold  PVDD_OV_LVL = 00b, 01b 0.6 0.9 1.2 V
VPVDD_OV_HYS PVDD overvoltage hysteresis Rising to falling threshold  PVDD_OV_LVL = 10b 2.0 2.2 2.4 V
tPVDD_OV_DG PVDD overvoltage deglitch time rising and falling edge 8 12 16 µs
VGVDD_UV GVDD undervoltage threshold VGVDD rising - after power up 7.0 7.8 V
VGVDD rising - power up only 7.5 8.1 V
VGVDD falling  6.8 7.6 V
VGVDD_UV_HYS GVDD undervoltage hysteresis Rising to falling threshold 185 215 245 mV
tGVDD_UV_DG GVDD undervoltage deglitch time rising and falling edge 8 12 16 µs
VGVDD_OV GVDD overvoltage threshold VGVDD rising 15 17 V
VGVDD_OV GVDD overvoltage threshold VGVDD falling 14.5 16.5 V
VGVDD_OV_HYS GVDD overvoltage hysteresis Rising to falling threshold 490 560 620 mV
tGVDD_OV_DG GVDD overvoltage deglitch time rising and falling edge 8 12 16 µs
VBST_UV Bootstrap undervoltage threshold VBSTx- VSHx; VBSTx rising; BST_UV_LVL = 1b 6.3 7.4 8.5 V
VBST_UV Bootstrap undervoltage threshold VBSTx- VSHx; VBSTx falling; BST_UV_LVL = 1b 6.1 7.2 8.3 V
VBST_UV Bootstrap undervoltage threshold VBSTx- VSHx; VBSTx rising; BST_UV_LVL = 0b 3.8 4.4 5 V
VBSTx- VSHx; VBSTx falling; BST_UV_LVL = 0b 3.65 4.2 4.8 V
VBST_UV_HYS Bootstrap undervoltage hysteresis Rising to falling threshold
BST_UV_LVL = 0b and 1b		 120 200 280 mV
tBST_UV_DG Bootstrap undervoltage deglitch time rising and falling edge 4 5 8 µs
VBST_OV Bootstrap overvoltage threshold VBSTx- VSHx; VBSTx rising 15.2 18 V
VBST_OV Bootstrap overvoltage threshold VBSTx- VSHx; VBSTx falling 15 17.8 V
VBST_OV_HYS Bootstrap overvoltage hysteresis 130 200 260 mV
tBST_OV_DG Bootstrap overvoltage deglitch time rising and falling edge 8 12 16 µs
VCP_UV VCP undervoltage threshold VCP - VDRAIN; rising 6 6.7 7.4 V
VCP_UV VCP undervoltage threshold VCP - VDRAIN; falling 5.7 6.4 7.1 V
tCP_UV_DG VCP undervoltage deglitch time rising and falling edge 8 12 16 µs
VCP_OV VCP overvoltage threshold VCP - VDRAIN; rising 14 17.0 V
VCP_OV VCP overvoltage threshold VCP - VDRAIN; falling 13.8 16.7 V
tCP_OV_DG VCP overvoltage deglitch time rising and falling edge 8 12 16 µs
VDRAIN_UV VDRAIN undervoltage threshold VVDRAIN rising 4.25 4.35 4.45 V
VDRAIN_UV VDRAIN undervoltage threshold VVDRAIN falling 4.05 4.15 4.25 V
VDRAIN_UV_HYS VDRAIN undervoltage hysteresis 170 190 210 mV
tVDRAIN_UV_DG VDRAIN undervoltage deglitch time rising and falling edge 8 12 16 µs
VDRAIN_OV VDRAIN overvoltage threshold VVDRAIN rising, VDRAIN_OV_LVL = 00b 28 31 V
VVDRAIN falling, VDRAIN_OV_LVL = 00b 27 30 V
VVDRAIN rising, VDRAIN_OV_LVL = 01b 33 36 V
VVDRAIN falling, VDRAIN_OV_LVL = 01b 32 35 V
VVDRAIN rising, VDRAIN_OV_LVL = 10b, 11b 50 55 V
VVDRAIN falling, VDRAIN_OV_LVL = 10b, 11b 48 353 V
VDRAIN_OV_HYS VDRAIN overvoltage hysteresis Rising to falling threshold, VDRAIN_OV_LVL = 00b, 01b 0.7 1.0 1.3 V
VDRAIN_OV_HYS VDRAIN overvoltage hysteresis Rising to falling threshold, VDRAIN_OV_LVL = 10b, 11b 2.0 2.3 2.6 V
tVDRAIN_OV_DG VDRAIN overvoltage deglitch time rising and falling edge 8 12 16 µs
PROTECTION CIRCUITS
VGS_LVL_H Gate voltage monitor threshold VGHx – VSHx, VGLx – VSLx, INLx / INHx=H;  VGS_LVL = 1'b1
 7 8.5 V
VGS_LVL_H Gate voltage monitor threshold VGHx – VSHx, VGLx – VSLx, INLx / INHx=H; VGS_LVL = 1'b0
 5 6.3 V
VGS_LVL_L Gate voltage monitor threshold VGHx – VSHx, VGLx – VSLx, INLx / INHx=L 1 2 V
tGS_DG VGS gate voltage monitor deglitch time VGS_DG = 000b
 0.3 0.6 0.8 µs
VGS_DG = 001b 0.6 1.0 1.3 µs
VGS_DG = 010b, 1.1 1.5 1.9 µs
VGS_DG = 011b, VGS_DG = 1xxb 1.6 2.0 2.5 µs
tGS_BLK VGS gate voltage monitor blanking time VGS_BLK = 000b 1.7 2.25 2.9 µs
VGS_BLK = 001b 2.4 3 3.6 µs
VGS_BLK = 010b 4.0 5 5.8 µs
VGS_BLK = 011b 5.9 7 8.2 µs
VGS_BLK = 100b, 101b, 110b, 111b 8.6 10 11.9 µs
VDS_LVL VDS overcurrent protection threshold VDS_LVL = 0000b; SLx = -0.2V to +2.0V. VDS_CM = 0b. 0.04 0.06 0.085 V
VDS_LVL = 0001b; SLx = -0.2V to +2.0V. VDS_CM = 0b. 0.06 0.08 0.11
VDS_LVL = 0010b; SLx = -0.3V to +2.0V. VDS_CM = 0b.

 0.075 0.10 0.13
VDS_LVL = 0011b; SLx = -0.3V to +2.0V. 0.09 0.12 0.16
VDS_LVL = 0100b; SLx = -0.3V to +2.0V. 0.13 0.16 0.20
VDS_LVL = 0101b; SLx = -0.3V to +2.0V. 0.2 0.24 0.29
VDS_LVL = 0110b; SLx = -0.3V to +2.0V. 0.27 0.32 0.385
VDS_LVL = 0111b; SLx = -0.3V to +2.0V. 0.35 0.4 0.48
VDS_LVL = 1000b; SLx = -0.3V to +2.0V. 0.44 0.5 0.58
VDS_LVL = 1001b; SLx = -0.3V to +2.0V. 0.59 0.67 0.77
VDS_LVL = 1010b; SLx = -0.3V to +2.0V. 0.75 0.83 0.96
VDS_LVL = 1011b; SLx = -0.3V to +2.0V. 0.90 1 1.15
VDS_LVL = 1100b; SLx = -0.3V to +2.0V. 1.13 1.25 1.42
VDS_LVL = 1101b; SLx = -0.3V to +2.0V. 1.36 1.5 1.70
VDS_LVL = 1110b;SLx = -0.3V to +2.0V. 1.58 1.75 1.98
VDS_LVL = 1111b;SLx = -0.3V to +2.0V. 1.81 2 2.26
tDS_CMP VDS comparator delay VDS (comparator input voltage) from 0V to max of VDS_LVL (comparator output rising),  delay time of internal comparator.  0.5 1.0 µs
tDS_CMP VDS comparator delay VDS (comparator input voltage) from VDRAIN to min of VDS_LVL (comparator output falling), delay time of internal comparator.  1.0 1.6 µs
tDS_DG VDS  overcurrent deglitch  VDS_DG = 000b
 0.3 0.5 0.8 µs
VDS_DG = 001b 0.7 1 1.3
VDS_DG = 010b 1.2 1.5 2.0
VDS_DG = 011b 1.5 2 2.5
VDS_DG = 100b 3.3 4 4.8
VDS_DG = 101b 5.2 6 7.3
VDS_DG = 110b, 111b 6.8 8 9.2
tDS_BLK VDS  overcurrent blanking time VDS_BLK = 000b 0 0.2 µs
VDS_BLK = 001b 0.4 0.5 0.7
VDS_BLK = 010b 0.7 1 1.5
VDS_BLK = 011b 1.4 2 2.6
VDS_BLK = 100b 5.0 6 7.2
VDS_BLK = 101b 6.8 8 9.4
VDS_BLK = 110b 8.4 10 11.9
VDS_BLK = 111b 10.1 12 13.9
VSENSE_LVL VSENSE overcurrent  threshold SNS_OCP_LVL = 000b : Input common mode voltage +/-2V 37 50 58 mV
SNS_OCP_LVL = 001b : Input common mode voltage +/-2V 62 75 84
SNS_OCP_LVL = 010b : Input common mode voltage +/-2V 87 100 110
SNS_OCP_LVL = 011b : Input common mode voltage +/-2V 112 125 135
SNS_OCP_LVL = 100b : Input common mode voltage +/-2V 135 150 165
SNS_OCP_LVL = 101b : Input common mode voltage +/-2V 185 200 215
SNS_OCP_LVL = 110b : Input common mode voltage +/-2V 280 300 320
SNS_OCP_LVL = 111b : Input common mode voltage +/-2V 475 500 525
tSENSE_DG VSENSE overcurrent deglitch time SNS_OCP_DG = 00b 1.5 2.0 2.5 µs
SNS_OCP_DG = 01b 3.0 4.0 5.0
SNS_OCP_DG = 10b 4.5 6.0 7.5
SNS_OCP_DG = 11b 8 10.0 12
VPHC_H Phase comparator high level threshold over VDRAIN (This is a ratio to VDRAIN voltage) PHC_THR = 0b 0.6 0.75 0.9
VPHC_H Phase comparator high level threshold over VDRAIN (This is a ratio to VDRAIN voltage) PHC_THR = 1b 0.37 0.52 0.67
VPHC_L Phase comparator low level threshold over VDRAIN (This is a ratio to VDRAIN voltage) PHC_THR = 0b 0.10 0.25 0.40
VPHC_L Phase comparator low level threshold over VDRAIN (This is a ratio to VDRAIN voltage) PHC_THR = 1b 0.33 0.48 0.63
tPHC_PD_HL Phase comparator propagation delay Propagation delay of phase comparator High to
Low from SHx to PHCx, Cload=20pF; SHx input
test condition 60V – 0V / 10ns (design target), From SHx = 88% to 15% of VDRAIN		 1.5 µs
tPHC_PD_LH Phase comparator propagation delay Propagation delay of phase comparator Low to
High from SHx to PHCx, Cload=20pF; SHx input
test condition 0V – 60V / 10 ns (design target), From SHx = 15% to 88% of VDRAIN		 1.5 µs
tPHC_OUT_DEG Phase comparator output deglitch time PHCOUT_DG_SEL = 1 0.8 1.0 1.4 µs
TOTW Thermal warning temperature TJ rising, OT_LVL = 0b; 125 150 °C
TOTW_HYS Thermal warning hysteresis 15 22 25 °C
tOTW_DEG Thermal warning deglitch 8 12 16 µs
TOTSD Thermal shutdown temperature TJ rising 155 180 °C
TOTSD_HYS Thermal shutdown hysteresis 16 23 27 °C
tOTSD_DEG Thermal shutdown deglitch 8 12 16 µs
tDRVN_SD Gate Drive Shutdown Sequence time 20 µs