JAJSGQ9A March   2018  – April 2019 DRV8343-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions—DRV8343H
    2.     Pin Functions—DRV8343S
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 SPI Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Three Phase Smart Gate Drivers
        1. 9.3.1.1 PWM Control Modes
          1. 9.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
          2. 9.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
          3. 9.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
          4. 9.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
          5. 9.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
          6. 9.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
          7. 9.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
          8. 9.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
        2. 9.3.1.2 Device Interface Modes
          1. 9.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 9.3.1.2.2 Hardware Interface
        3. 9.3.1.3 Gate Driver Voltage Supplies
        4. 9.3.1.4 Smart Gate Drive Architecture
          1. 9.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 9.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 9.3.1.4.3 Propagation Delay
          4. 9.3.1.4.4 MOSFET VDS Monitors
          5. 9.3.1.4.5 VDRAIN Sense Pin
          6. 9.3.1.4.6 nFAULT Pin
      2. 9.3.2 DVDD Linear Voltage Regulator
      3. 9.3.3 Pin Diagrams
      4. 9.3.4 Low-Side Current Sense Amplifiers
        1. 9.3.4.1 Bidirectional Current Sense Operation
        2. 9.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 9.3.4.3 Amplifier Calibration Modes
        4. 9.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 9.3.5 Gate Driver Protective Circuits
        1. 9.3.5.1  VM Supply Undervoltage Lockout (UVLO)
        2. 9.3.5.2  VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 9.3.5.3  MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 9.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 9.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 9.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 9.3.5.4  VSENSE Overcurrent Protection (SEN_OCP)
          1. 9.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 9.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 9.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b)
        5. 9.3.5.5  Gate Driver Fault (GDF)
        6. 9.3.5.6  Thermal Warning (OTW)
        7. 9.3.5.7  Thermal Shutdown (OTSD)
          1. 9.3.5.7.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 9.3.5.7.2 Automatic Recovery (OTSD_MODE = 1b)
        8. 9.3.5.8  Open Load Detection (OLD)
          1. 9.3.5.8.1 Open Load Detection in Passive Mode (OLP)
            1. 9.3.5.8.1.1 OLP Steps
          2. 9.3.5.8.2 Open Load Detection in Active Mode (OLA)
        9. 9.3.5.9  Offline Shorts Diagnostics
          1. 9.3.5.9.1 Offline Short-to-Supply Diagnostic (SHT_BAT)
          2. 9.3.5.9.2 Offline Short-to-Ground Diagnostic (SHT_GND)
        10. 9.3.5.10 Reverse Supply Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Gate Driver Functional Modes
        1. 9.4.1.1 Sleep Mode
        2. 9.4.1.2 Operating Mode
        3. 9.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 SPI
          1. 9.5.1.1.1 SPI Format
    6. 9.6 Register Maps
      1. 9.6.1 Status Registers
        1. 9.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]
          1. Table 16. FAULT Status Register Field Descriptions
        2. 9.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]
          1. Table 17. DIAG Status A Register Field Descriptions
        3. 9.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]
          1. Table 18. DIAG Status B Register Field Descriptions
        4. 9.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]
          1. Table 19. DIAG Status C Register Field Descriptions
      2. 9.6.2 Control Registers
        1. 9.6.2.1  IC1 Control Register (Address = 0x04) [reset = 0x00]
          1. Table 21. IC1 Control Field Descriptions
        2. 9.6.2.2  IC2 Control Register (address = 0x05) [reset = 0x40]
          1. Table 22. IC2 Control Field Descriptions
        3. 9.6.2.3  IC3 Control Register (Address = 0x06) [reset = 0xFF]
          1. Table 23. IC3 Control Field Descriptions
        4. 9.6.2.4  IC4 Control Register (Address = 0x07) [reset = 0xFF]
          1. Table 24. IC4 Control Field Descriptions
        5. 9.6.2.5  IC5 Control Register (Address = 0x08) [reset = 0xFF]
          1. Table 25. IC5 Control Field Descriptions
        6. 9.6.2.6  IC6 Control Register (Address = 0x09) [reset = 0x99]
          1. Table 26. IC6 Control Field Descriptions
        7. 9.6.2.7  IC7 Control Register (Address = 0x0A) [reset = 0x99]
          1. Table 27. IC7 Control Field Descriptions
        8. 9.6.2.8  IC8 Control Register (Address = 0x0B) [reset = 0x99]
          1. Table 28. IC8 Control Field Descriptions
        9. 9.6.2.9  IC9 Control Register (Address = 0x0C) [reset = 0x2F]
          1. Table 29. IC9 Control Field Descriptions
        10. 9.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
          1. Table 30. IC10 Control Field Descriptions
        11. 9.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
          1. Table 31. IC11 Control Field Descriptions
        12. 9.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
          1. Table 32. IC12 Control Field Descriptions
        13. 9.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
          1. Table 33. IC13 Control Field Descriptions
        14. 9.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
          1. Table 34. IC14 Control Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Primary Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 External MOSFET Support
            1. 10.2.1.2.1.1 Example
          2. 10.2.1.2.2 IDRIVE Configuration
            1. 10.2.1.2.2.1 Example
          3. 10.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 10.2.1.2.3.1 Example
          4. 10.2.1.2.4 Sense Amplifier Bidirectional Configuration
            1. 10.2.1.2.4.1 Example
          5. 10.2.1.2.5 External Components
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Application With One Sense Amplifier
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 10.2.2.2.1.1 Example
            2. 10.2.2.2.1.2 Unused pins
          2. 10.2.2.2.2 External Components
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Consideration in Generator Mode
    2. 11.2 Bulk Capacitance Sizing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Overview

The DRV8343-Q1 device is an integrated gate driver for three-phase motor driver automotive applications. These devices decrease system complexity by integrating three independent half-bridge gate drivers, charge pump, and linear regulator for the supply voltages of the high-side and low-side gate drivers.The device also integrates three current shunt (or current sense) amplifiers. A standard serial peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring the most common settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A source, 2-A sink peak currents. A doubler charge pump generates the supply voltage of the high-side gate drive. This charge pump architecture regulates the VCP output voltage for driving high-side power MOSFET. The supply voltage of the low-side gate driver is generated using a linear regulator from the VM power supply that regulates for driving low-side power MOSFET. A Smart Gate Drive architecture provides the ability to dynamically adjust the strength of the gate drive output current which lets the gate driver control the VDS switching speed of the power MOSFET. This feature lets the user remove the external gate drive resistors and diodes, reducing the component count in the bill of materials (BOM), cost, and area of the printed circuit board (PCB). The architecture also uses an internal state machine to protect against short-circuit events in the gate driver, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.

The DRV8343-Q1 device integrates three bidirectional current sense amplifiers for monitoring the current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the current sense amplifiers can be adjusted through the SPI or hardware interface. The SPI method providing additional flexibility to adjust the output bias point.

In addition to the high level of device integration, the DRV8343-Q1 device provides a wide range of integrated protection features. These features include power supply undervoltage lockout (UVLO), charge pump undervoltage lockout (CPUV), short to supply (SHT_BAT), short-to-ground (SHT_GND), open-load detection (OLD), VDS overcurrent monitoring (OCP), gate driver short-circuit detection (GDF), and overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.

The DRV8343-Q1 device is available in a 0.5-mm pin pitch, 7 × 7 mm, HTQFP surface-mount package.