JAJSGQ9A March   2018  – April 2019 DRV8343-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions—DRV8343H
    2.     Pin Functions—DRV8343S
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 SPI Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Three Phase Smart Gate Drivers
        1. 9.3.1.1 PWM Control Modes
          1. 9.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
          2. 9.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
          3. 9.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
          4. 9.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
          5. 9.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
          6. 9.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
          7. 9.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
          8. 9.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
        2. 9.3.1.2 Device Interface Modes
          1. 9.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 9.3.1.2.2 Hardware Interface
        3. 9.3.1.3 Gate Driver Voltage Supplies
        4. 9.3.1.4 Smart Gate Drive Architecture
          1. 9.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 9.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 9.3.1.4.3 Propagation Delay
          4. 9.3.1.4.4 MOSFET VDS Monitors
          5. 9.3.1.4.5 VDRAIN Sense Pin
          6. 9.3.1.4.6 nFAULT Pin
      2. 9.3.2 DVDD Linear Voltage Regulator
      3. 9.3.3 Pin Diagrams
      4. 9.3.4 Low-Side Current Sense Amplifiers
        1. 9.3.4.1 Bidirectional Current Sense Operation
        2. 9.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 9.3.4.3 Amplifier Calibration Modes
        4. 9.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 9.3.5 Gate Driver Protective Circuits
        1. 9.3.5.1  VM Supply Undervoltage Lockout (UVLO)
        2. 9.3.5.2  VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 9.3.5.3  MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 9.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 9.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 9.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 9.3.5.4  VSENSE Overcurrent Protection (SEN_OCP)
          1. 9.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 9.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 9.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b)
        5. 9.3.5.5  Gate Driver Fault (GDF)
        6. 9.3.5.6  Thermal Warning (OTW)
        7. 9.3.5.7  Thermal Shutdown (OTSD)
          1. 9.3.5.7.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 9.3.5.7.2 Automatic Recovery (OTSD_MODE = 1b)
        8. 9.3.5.8  Open Load Detection (OLD)
          1. 9.3.5.8.1 Open Load Detection in Passive Mode (OLP)
            1. 9.3.5.8.1.1 OLP Steps
          2. 9.3.5.8.2 Open Load Detection in Active Mode (OLA)
        9. 9.3.5.9  Offline Shorts Diagnostics
          1. 9.3.5.9.1 Offline Short-to-Supply Diagnostic (SHT_BAT)
          2. 9.3.5.9.2 Offline Short-to-Ground Diagnostic (SHT_GND)
        10. 9.3.5.10 Reverse Supply Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Gate Driver Functional Modes
        1. 9.4.1.1 Sleep Mode
        2. 9.4.1.2 Operating Mode
        3. 9.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 SPI
          1. 9.5.1.1.1 SPI Format
    6. 9.6 Register Maps
      1. 9.6.1 Status Registers
        1. 9.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]
          1. Table 16. FAULT Status Register Field Descriptions
        2. 9.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]
          1. Table 17. DIAG Status A Register Field Descriptions
        3. 9.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]
          1. Table 18. DIAG Status B Register Field Descriptions
        4. 9.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]
          1. Table 19. DIAG Status C Register Field Descriptions
      2. 9.6.2 Control Registers
        1. 9.6.2.1  IC1 Control Register (Address = 0x04) [reset = 0x00]
          1. Table 21. IC1 Control Field Descriptions
        2. 9.6.2.2  IC2 Control Register (address = 0x05) [reset = 0x40]
          1. Table 22. IC2 Control Field Descriptions
        3. 9.6.2.3  IC3 Control Register (Address = 0x06) [reset = 0xFF]
          1. Table 23. IC3 Control Field Descriptions
        4. 9.6.2.4  IC4 Control Register (Address = 0x07) [reset = 0xFF]
          1. Table 24. IC4 Control Field Descriptions
        5. 9.6.2.5  IC5 Control Register (Address = 0x08) [reset = 0xFF]
          1. Table 25. IC5 Control Field Descriptions
        6. 9.6.2.6  IC6 Control Register (Address = 0x09) [reset = 0x99]
          1. Table 26. IC6 Control Field Descriptions
        7. 9.6.2.7  IC7 Control Register (Address = 0x0A) [reset = 0x99]
          1. Table 27. IC7 Control Field Descriptions
        8. 9.6.2.8  IC8 Control Register (Address = 0x0B) [reset = 0x99]
          1. Table 28. IC8 Control Field Descriptions
        9. 9.6.2.9  IC9 Control Register (Address = 0x0C) [reset = 0x2F]
          1. Table 29. IC9 Control Field Descriptions
        10. 9.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
          1. Table 30. IC10 Control Field Descriptions
        11. 9.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
          1. Table 31. IC11 Control Field Descriptions
        12. 9.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
          1. Table 32. IC12 Control Field Descriptions
        13. 9.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
          1. Table 33. IC13 Control Field Descriptions
        14. 9.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
          1. Table 34. IC14 Control Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Primary Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 External MOSFET Support
            1. 10.2.1.2.1.1 Example
          2. 10.2.1.2.2 IDRIVE Configuration
            1. 10.2.1.2.2.1 Example
          3. 10.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 10.2.1.2.3.1 Example
          4. 10.2.1.2.4 Sense Amplifier Bidirectional Configuration
            1. 10.2.1.2.4.1 Example
          5. 10.2.1.2.5 External Components
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Application With One Sense Amplifier
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 10.2.2.2.1.1 Example
            2. 10.2.2.2.1.2 Unused pins
          2. 10.2.2.2.2 External Components
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Consideration in Generator Mode
    2. 11.2 Bulk Capacitance Sizing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1.4.6 nFAULT Pin

The nFAULT pin has an open-drain output and should be pulled up to a 5 V or 3.3 V supply. When a fault is detected, the nFAULT line is logic low. For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the Application and Implementation section). For a 5-V pullup an external 5-V supply must be used.

DRV8343-Q1 drv8873-q1-nfault-block-diagram.gifFigure 23. nFAULT Pin

During the power-up sequence, or when going from sleep mode, the digital core of the device is enabled to a VM voltage of approximately 3.3 V and the device is fully operational after VM exceeds 5.5 V. After the digital core is alive if the VM does not exceed 5.5 V within 100-µs the device will flag a UVLO fault. In the H/W device, the nFAULT pin is driven low. In the SPI device, the FAULT and ULVO bits will be latched high