JAJSFY1A August   2018  – June  2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions—32-Pin DRV8350 Devices
    2.     Pin Functions—48-Pin DRV8350R Devices
    3.     Pin Functions—40-Pin DRV8353 Devices
    4.     Pin Functions—48-Pin DRV8353R Devices
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 SPI Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Three Phase Smart Gate Drivers
        1. 9.3.1.1 PWM Control Modes
          1. 9.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 9.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 9.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 9.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 9.3.1.2 Device Interface Modes
          1. 9.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 9.3.1.2.2 Hardware Interface
        3. 9.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
        4. 9.3.1.4 Smart Gate Drive Architecture
          1. 9.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 9.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 9.3.1.4.3 Propagation Delay
          4. 9.3.1.4.4 MOSFET VDS Monitors
          5. 9.3.1.4.5 VDRAIN Sense and Reference Pin
      2. 9.3.2 DVDD Linear Voltage Regulator
      3. 9.3.3 Pin Diagrams
      4. 9.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
        1. 9.3.4.1 Bidirectional Current Sense Operation
        2. 9.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 9.3.4.3 Amplifier Calibration Modes
        4. 9.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 9.3.5 Step-Down Buck Regulator
        1. 9.3.5.1 Functional Block Diagram
        2. 9.3.5.2 Feature Description
          1. 9.3.5.2.1 Control Circuit Overview
          2. 9.3.5.2.2 Start-Up Regulator (VCC)
          3. 9.3.5.2.3 Regulation Comparator
          4. 9.3.5.2.4 Overvoltage Comparator
          5. 9.3.5.2.5 On-Time Generator and Shutdown
          6. 9.3.5.2.6 Current Limit
          7. 9.3.5.2.7 N-Channel Buck Switch and Driver
          8. 9.3.5.2.8 Thermal Protection
      6. 9.3.6 Gate Driver Protective Circuits
        1. 9.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. 9.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. 9.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 9.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 9.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 9.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 9.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 9.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 9.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 9.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 9.3.6.5 Gate Driver Fault (GDF)
        6. 9.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
        7. 9.3.6.7 Thermal Warning (OTW)
        8. 9.3.6.8 Thermal Shutdown (OTSD)
        9. 9.3.6.9 Fault Response Table
    4. 9.4 Device Functional Modes
      1. 9.4.1 Gate Driver Functional Modes
        1. 9.4.1.1 Sleep Mode
        2. 9.4.1.2 Operating Mode
        3. 9.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 9.4.2 Buck Regulator Functional Modes
        1. 9.4.2.1 Shutdown Mode
        2. 9.4.2.2 Active Mode
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 SPI
          1. 9.5.1.1.1 SPI Format
    6. 9.6 Register Maps
      1. 9.6.1 Status Registers
        1. 9.6.1.1 Fault Status Register 1 (address = 0x00h)
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 9.6.1.2 Fault Status Register 2 (address = 0x01h)
          1. Table 12. Fault Status Register 2 Field Descriptions
      2. 9.6.2 Control Registers
        1. 9.6.2.1 Driver Control Register (address = 0x02h)
          1. Table 14. Driver Control Field Descriptions
        2. 9.6.2.2 Gate Drive HS Register (address = 0x03h)
          1. Table 15. Gate Drive HS Field Descriptions
        3. 9.6.2.3 Gate Drive LS Register (address = 0x04h)
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 9.6.2.4 OCP Control Register (address = 0x05h)
          1. Table 17. OCP Control Field Descriptions
        5. 9.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
          1. Table 18. CSA Control Field Descriptions
        6. 9.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
          1. Table 19. Driver Configuration Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Primary Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 External MOSFET Support
            1. 10.2.1.2.1.1 MOSFET Example
          2. 10.2.1.2.2 IDRIVE Configuration
            1. 10.2.1.2.2.1 IDRIVE Example
          3. 10.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 10.2.1.2.3.1 VDS Overcurrent Example
          4. 10.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
            1. 10.2.1.2.4.1 Sense-Amplifier Example
          5. 10.2.1.2.5 Single Supply Power Dissipation
          6. 10.2.1.2.6 Single Supply Power Dissipation Example
          7. 10.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Alternative Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 10.2.2.2.1.1 Sense-Amplifier Example
            2. 10.2.2.2.1.2 Dual Supply Power Dissipation
            3. 10.2.2.2.1.3 Dual Supply Power Dissipation Example
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance Sizing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Buck-Regulator Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

DRV8350H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
DRV8350S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View

Pin Functions—32-Pin DRV8350 Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8350H DRV8350S
CPH 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 32 32 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DVDD 29 29 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally.
ENABLE 22 22 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used to reset fault conditions.
GHA 5 5 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 12 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 13 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 7 7 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 30 30 PWR Device primary ground. Connect to system ground.
IDRIVE 19 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 23 23 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 25 25 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 27 27 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 24 24 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 21 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source.
VCP 4 4 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 3 3 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 31 31 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM 2 2 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8350RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8350RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions—48-Pin DRV8350R Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8350RH DRV8350RS
AGND 27 27 PWR Device analog ground. Connect to system ground.
BST 45 45 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DGND 41 41 PWR Device digital ground. Connect to system ground.
DVDD 40 40 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally.
ENABLE 33 33 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 48 48 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 1 1 PWR Device primary ground. Connect to system ground.
IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 12 12 NC No internal connection. This pin can be left floating or connected to system ground.
NC 13 13 NC No internal connection. This pin can be left floating or connected to system ground.
NC 22 22 NC No internal connection. This pin can be left floating or connected to system ground.
NC 23 23 NC No internal connection. This pin can be left floating or connected to system ground.
NC 24 24 NC No internal connection. This pin can be left floating or connected to system ground.
NC 25 25 NC No internal connection. This pin can be left floating or connected to system ground.
NC 26 26 NC No internal connection. This pin can be left floating or connected to system ground.
NC 32 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.
RCL 46 46 I Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD 47 47 I On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 11 11 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 14 14 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 21 21 I Low-side source sense input. Connect to the low-side power MOSFET source.
SW 42 42 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC 44 44 PWR 7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins.
VCP 7 7 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 6 6 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 2 2 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN 43 43 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
VM 5 5 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8353H RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
DRV8353S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View

Pin Functions—40-Pin DRV8353 Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8353H DRV8353S
AGND 25 25 PWR Device analog ground. Connect to system ground.
CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DVDD 38 38 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally.
ENABLE 31 31 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
GAIN 30 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 39 39 PWR Device power ground. Connect to system ground.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 28 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 27 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 26 26 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 30 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 29 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 28 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 27 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Shunt amplifier output.
SOB 22 22 O Shunt amplifier output.
SOC 21 21 O Shunt amplifier output.
SPA 9 9 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 12 12 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 19 19 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 4 4 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 29 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 40 40 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM 3 3 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF 24 24 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8353RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8353RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions—48-Pin DRV8353R Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8353RH DRV8353RS
AGND 27 27 PWR Device analog ground. Connect to system ground.
BST 45 45 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DGND 41 41 PWR Device ground. Connect to system ground.
DVDD 40 40 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally.
ENABLE 33 33 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 48 48 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GAIN 32 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 1 1 PWR Device power ground. Connect to system ground.
GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.
RCL 46 46 I Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD 47 47 I On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 12 12 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 13 13 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 22 22 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 25 25 O Shunt amplifier output.
SOB 24 24 O Shunt amplifier output.
SOC 23 23 O Shunt amplifier output.
SPA 11 11 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 14 14 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 21 21 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SW 42 42 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC 44 44 PWR 7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins.
VCP 7 7 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 6 6 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 2 2 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN 43 43 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM 5 5 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF 26 26 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain