SLVSHQ2 December   2024 DRV8351-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 Gate Driver Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Bootstrap Capacitor and GVDD Capacitor Selection

The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for normal operation. Equation 1 calculates the maximum allowable voltage drop across the bootstrap capacitor:

Equation 1. DRV8351-SEP

=12V – 0.85V – 4.5V = 6.65V

where

  • VGVDD is the supply voltage of the gate drive
  • VBOOTD is the forward voltage drop of the bootstrap diode
  • VBSTUV is the threshold of the bootstrap undervoltage lockout

In this example the allowed voltage drop across bootstrap capacitor is 6.65V. It is generally recommended that ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible. Many commercial, industrial, and automotive applications use ripple values between 0.5V to 1V.

The total charge needed per switching cycle can be estimated with Equation 2:

Equation 2. DRV8351-SEP

=48nC + 220μA/20kHz = 50nC + 11nC = 59nC

where

  • QG is the total MOSFET gate charge
  • ILBS_TRAN is the bootstrap pin leakage current
  • fSW is the is the PWM frequency

The minimum bootstrap capacitor an then be estimated as below assuming 1V ΔVBSTx:

Equation 3. DRV8351-SEP

= 59nC / 1V = 59nF

The calculated value of the minimum bootstrap capacitor is 59nF. It should be noted that this value of capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than the calculated value to allow for situations where the power stage may skip pulse due to various transient conditions. It is recommended to use a 100nF bootstrap capacitor in this example. It is also recommended to include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.

Equation 4. DRV8351-SEP

= 10*100nF= 1μF

For this example application choose 1µF CGVDD capacitor. Choose a capacitor with a voltage rating at least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of the system.