JAJSFY1A August   2018  – June  2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions—32-Pin DRV8350 Devices
    2.     Pin Functions—48-Pin DRV8350R Devices
    3.     Pin Functions—40-Pin DRV8353 Devices
    4.     Pin Functions—48-Pin DRV8353R Devices
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 SPI Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Three Phase Smart Gate Drivers
        1. 9.3.1.1 PWM Control Modes
          1. 9.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 9.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 9.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 9.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 9.3.1.2 Device Interface Modes
          1. 9.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 9.3.1.2.2 Hardware Interface
        3. 9.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
        4. 9.3.1.4 Smart Gate Drive Architecture
          1. 9.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 9.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 9.3.1.4.3 Propagation Delay
          4. 9.3.1.4.4 MOSFET VDS Monitors
          5. 9.3.1.4.5 VDRAIN Sense and Reference Pin
      2. 9.3.2 DVDD Linear Voltage Regulator
      3. 9.3.3 Pin Diagrams
      4. 9.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
        1. 9.3.4.1 Bidirectional Current Sense Operation
        2. 9.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 9.3.4.3 Amplifier Calibration Modes
        4. 9.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 9.3.5 Step-Down Buck Regulator
        1. 9.3.5.1 Functional Block Diagram
        2. 9.3.5.2 Feature Description
          1. 9.3.5.2.1 Control Circuit Overview
          2. 9.3.5.2.2 Start-Up Regulator (VCC)
          3. 9.3.5.2.3 Regulation Comparator
          4. 9.3.5.2.4 Overvoltage Comparator
          5. 9.3.5.2.5 On-Time Generator and Shutdown
          6. 9.3.5.2.6 Current Limit
          7. 9.3.5.2.7 N-Channel Buck Switch and Driver
          8. 9.3.5.2.8 Thermal Protection
      6. 9.3.6 Gate Driver Protective Circuits
        1. 9.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. 9.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. 9.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 9.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 9.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 9.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 9.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 9.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 9.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 9.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 9.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 9.3.6.5 Gate Driver Fault (GDF)
        6. 9.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
        7. 9.3.6.7 Thermal Warning (OTW)
        8. 9.3.6.8 Thermal Shutdown (OTSD)
        9. 9.3.6.9 Fault Response Table
    4. 9.4 Device Functional Modes
      1. 9.4.1 Gate Driver Functional Modes
        1. 9.4.1.1 Sleep Mode
        2. 9.4.1.2 Operating Mode
        3. 9.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 9.4.2 Buck Regulator Functional Modes
        1. 9.4.2.1 Shutdown Mode
        2. 9.4.2.2 Active Mode
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 SPI
          1. 9.5.1.1.1 SPI Format
    6. 9.6 Register Maps
      1. 9.6.1 Status Registers
        1. 9.6.1.1 Fault Status Register 1 (address = 0x00h)
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 9.6.1.2 Fault Status Register 2 (address = 0x01h)
          1. Table 12. Fault Status Register 2 Field Descriptions
      2. 9.6.2 Control Registers
        1. 9.6.2.1 Driver Control Register (address = 0x02h)
          1. Table 14. Driver Control Field Descriptions
        2. 9.6.2.2 Gate Drive HS Register (address = 0x03h)
          1. Table 15. Gate Drive HS Field Descriptions
        3. 9.6.2.3 Gate Drive LS Register (address = 0x04h)
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 9.6.2.4 OCP Control Register (address = 0x05h)
          1. Table 17. OCP Control Field Descriptions
        5. 9.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
          1. Table 18. CSA Control Field Descriptions
        6. 9.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
          1. Table 19. Driver Configuration Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Primary Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 External MOSFET Support
            1. 10.2.1.2.1.1 MOSFET Example
          2. 10.2.1.2.2 IDRIVE Configuration
            1. 10.2.1.2.2.1 IDRIVE Example
          3. 10.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 10.2.1.2.3.1 VDS Overcurrent Example
          4. 10.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
            1. 10.2.1.2.4.1 Sense-Amplifier Example
          5. 10.2.1.2.5 Single Supply Power Dissipation
          6. 10.2.1.2.6 Single Supply Power Dissipation Example
          7. 10.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Alternative Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 10.2.2.2.1.1 Sense-Amplifier Example
            2. 10.2.2.2.1.2 Dual Supply Power Dissipation
            3. 10.2.2.2.1.3 Dual Supply Power Dissipation Example
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance Sizing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Buck-Regulator Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1.4.4 MOSFET VDS Monitors

The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the device VDS fault mode.

The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three current-shunt amplifiers (DRV8353 and DRV8353R), the low-side VDS monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the external half-bridges. On device options without the current shunt amplifiers (DRV8350 and DRV8350R) the low-side VDS monitor measures between the SHx and SLx pins.

For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor stays between the VDRAIN and SHx pins.

The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on hardware interface devices. Additional information on the VDS monitor levels are described in the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.

DRV8350 DRV8350R DRV8353 DRV8353R drv835x-vds-no-amps.gifFigure 34. DRV8350 and DRV8350R VDS Monitors
DRV8350 DRV8350R DRV8353 DRV8353R drv835x-vds-amps.gifFigure 35. DRV8353 and DRV8353R VDS Monitors