JAJSKV6D August   2020  – April 2024 DRV8714-Q1 , DRV8718-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 5.2 VQFN (RHA) 40-Pin Package and Pin Functions
    3. 5.3 HTQFP (PHP) 48-Pin Package and Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Control Modes
        1. 7.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 7.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 7.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
          1. 7.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
          1. 7.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 7.3.4.4 Propagation Delay Reduction (PDR)
          1. 7.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 7.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 7.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 7.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 7.3.4.6 Closed Loop Slew Time Control (STC)
          1. 7.3.4.6.1 STC Control Loop Setup
      5. 7.3.5 Tripler (Dual-Stage) Charge Pump
      6. 7.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 7.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 7.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 7.3.8.3  Fault Reset (CLR_FLT)
        4. 7.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 7.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 7.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 7.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 7.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 7.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 7.3.8.10 Thermal Warning (OTW)
        11. 7.3.8.11 Thermal Shutdown (OTSD)
        12. 7.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 7.3.8.13 Watchdog Timer
        14. 7.3.8.14 Fault Detection and Response Summary Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
  9. 8 Register Maps
    1. 8.1 DRV8718-Q1 Register Map
    2. 8.2 DRV8714-Q1 Register Map
    3. 8.3 DRV8718-Q1 Register Descriptions
      1. 8.3.1 DRV8718-Q1_STATUS Registers
      2. 8.3.2 DRV8718-Q1_CONTROL Registers
      3. 8.3.3 DRV8718-Q1_CONTROL_ADV Registers
      4. 8.3.4 DRV8718-Q1_STATUS_ADV Registers
    4. 8.4 DRV8714-Q1 Register Descriptions
      1. 8.4.1 DRV8714-Q1_STATUS Registers
      2. 8.4.2 DRV8714-Q1_CONTROL Registers
      3. 8.4.3 DRV8714-Q1_CONTROL_ADV Registers
      4. 8.4.4 DRV8714-Q1_STATUS_ADV Registers
  10. 9  Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device Documentation and Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documents
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 DRV8714-Q1_STATUS Registers

Table 8-74 lists the DRV8714-Q1_STATUS registers. All register offset addresses not listed in Table 8-74 should be considered as reserved locations and the register contents should not be modified.

Table 8-74 DRV8714-Q1_STATUS Registers
Address Acronym Register Name Section
0h IC_STAT1 Global fault and warning status indicators Go
1h VDS_STAT1 Half-bridge 1-4 VDS overcurrent fault status indicators Go
3h VGS_STAT1 Half-bridge 1-4 VGS gate fault status indicators Go
5h IC_STAT2 Voltage, temperature and interface fault status indicators Go
6h IC_STAT3 Device variant ID status register Go

Complex bit access types are encoded to fit into small table cells. Table 8-75 shows the codes that are used for access types in this section.

Table 8-75 DRV8714-Q1_STATUS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
- n Value after reset or the default value

8.4.1.1 IC_STAT1 Register (Address = 0h) [Reset = C0h]

IC_STAT1 is shown in Figure 8-62 and described in Table 8-76.

Return to the Summary Table.

Status register for global fault and warning indicators. Detailed fault information is available in remaining status registers.

Figure 8-62 IC_STAT1 Register
7 6 5 4 3 2 1 0
SPI_OK POR FAULT WARN DS_GS UV OV OT_WD_AGD
R-1b R-1b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-76 IC_STAT1 Register Field Descriptions
Bit Field Type Reset Description
7 SPI_OK R 1b Indicates if a SPI communications fault has been detected.
0b = One or multiple of SCLK_FLT in the prior frames.
1b = No SPI fault has been detected
6 POR R 1b Indicates power-on-reset condition.
0b = No power-on-reset condition detected.
1b = Power-on reset condition detected.
5 FAULT R 0b Fault indicator. Mirrors nFAULT pin.
4 WARN R 0b Warning indicator.
3 DS_GS R 0b Logic OR of VDS and VGS fault indicators.
2 UV R 0b Undervoltage indicator.
1 OV R 0b Overvoltage indicator.
0 OT_WD_AGD R 0b Logic OR of OTW, OTSD, WD_FLT, IDIR_WARN, PCHR_WARN, PDCHR_WARN, and STC_WARN indicators.

8.4.1.2 VDS_STAT1 Register (Address = 1h) [Reset = 0h]

VDS_STAT1 is shown in Figure 8-63 and described in Table 8-77.

Return to the Summary Table.

Status register for the specific MOSFET VDS overcurrent fault indication for half-bridges 1-4.

Figure 8-63 VDS_STAT1 Register
7 6 5 4 3 2 1 0
VDS_H1 VDS_L1 VDS_H2 VDS_L2 VDS_H3 VDS_L3 VDS_H4 VDS_L4
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-77 VDS_STAT1 Register Field Descriptions
Bit Field Type Reset Description
7 VDS_H1 R 0b Indicates VDS overcurrent fault on the high-side 1 MOSFET.
6 VDS_L1 R 0b Indicates VDS overcurrent fault on the low-side 1 MOSFET.
5 VDS_H2 R 0b Indicates VDS overcurrent fault on the high-side 2 MOSFET.
4 VDS_L2 R 0b Indicates VDS overcurrent fault on the low-side 2 MOSFET.
3 VDS_H3 R 0b Indicates VDS overcurrent fault on the high-side 3 MOSFET.
2 VDS_L3 R 0b Indicates VDS overcurrent fault on the low-side 3 MOSFET.
1 VDS_H4 R 0b Indicates VDS overcurrent fault on the high-side 4 MOSFET.
0 VDS_L4 R 0b Indicates VDS overcurrent fault on the low-side 4 MOSFET.

8.4.1.3 VGS_STAT1 Register (Address = 3h) [Reset = 0h]

VGS_STAT1 is shown in Figure 8-64 and described in Table 8-78.

Return to the Summary Table.

Status register for the specific MOSFET VGS gate fault indication for half-bridges 1-4.

Figure 8-64 VGS_STAT1 Register
7 6 5 4 3 2 1 0
VGS_H1 VGS_L1 VGS_H2 VGS_L2 VGS_H3 VGS_L3 VGS_H4 VGS_L4
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-78 VGS_STAT1 Register Field Descriptions
Bit Field Type Reset Description
7 VGS_H1 R 0b Indicates VGS gate fault on the high-side 1 MOSFET.
6 VGS_L1 R 0b Indicates VGS gate fault on the low-side 1 MOSFET.
5 VGS_H2 R 0b Indicates VGS gate fault on the high-side 2 MOSFET.
4 VGS_L2 R 0b Indicates VGS gate fault on the low-side 2 MOSFET.
3 VGS_H3 R 0b Indicates VGS gate fault on the high-side 3 MOSFET.
2 VGS_L3 R 0b Indicates VGS gate fault on the low-side 3 MOSFET.
1 VGS_H4 R 0b Indicates VGS gate fault on the high-side 4 MOSFET.
0 VGS_L4 R 0b Indicates VGS gate fault on the low-side 4 MOSFET.

8.4.1.4 IC_STAT2 Register (Address = 5h) [Reset = 0h]

IC_STAT2 is shown in Figure 8-65 and described in Table 8-79.

Return to the Summary Table.

Status register for specific undervoltage, overvoltage, overtemperature, and interface fault indications.

Figure 8-65 IC_STAT2 Register
7 6 5 4 3 2 1 0
PVDD_UV PVDD_OV VCP_UV OTW OTSD WD_FLT SCLK_FLT RESERVED
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-79 IC_STAT2 Register Field Descriptions
Bit Field Type Reset Description
7 PVDD_UV R 0b Indicates undervoltage fault on PVDD pin.
6 PVDD_OV R 0b Indicates overvoltage fault on PVDD pin.
5 VCP_UV R 0b Indicates undervoltage fault on VCP pin.
4 OTW R 0b Indicates overtemperature warning.
3 OTSD R 0b Indicates overtemperature shutdown.
2 WD_FLT R 0b Indicated watchdog timer fault.
1 SCLK_FLT R 0b Indicates SPI clock (frame) fault when the number of SCLK pulses in a transaction frame are not equal to 16. Not reported on FAULT or nFAULT pin.
0 RESERVED R 0b Reserved

8.4.1.5 IC_STAT3 Register (Address = 6h) [Reset = 4h]

IC_STAT3 is shown in Figure 8-66 and described in Table 8-80.

Return to the Summary Table.

Status register with device ID for either DRV8718-Q1 or DRV8714-Q1.

Figure 8-66 IC_STAT3 Register
7 6 5 4 3 2 1 0
RESERVED IC_ID
R-0000b R-0100b
Table 8-80 IC_STAT3 Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved
3-0 IC_ID R 0100b Device identification field.
0100b = DRV8714-Q1, 4 half-bridge gate driver.
1000b = DRV8718-Q1, 8 half-bridge gate driver.