JAJS491K July   2008  – March 2021 DRV8800 , DRV8801

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Logic Inputs
      2. 8.3.2  VREG (DRV8800 Only)
      3. 8.3.3  VPROPI (DRV8801 Only)
        1. 8.3.3.1 Connecting VPROPI Output to ADC
      4. 8.3.4  Charge Pump
      5. 8.3.5  Shutdown
      6. 8.3.6  Low-Power Mode
      7. 8.3.7  Braking
      8. 8.3.8  Diagnostic Output
      9. 8.3.9  Thermal Shutdown (TSD)
      10. 8.3.10 Overcurrent Protection
      11. 8.3.11 SENSE
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
        1. 8.4.1.1 Slow-Decay SR (Brake Mode)
        2. 8.4.1.2 Fast Decay With Synchronous Rectification
          1. 8.4.1.2.1 34
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Motor Voltage
        2. 9.2.2.2 Power Dissipation
        3. 9.2.2.3 Thermal Considerations
          1. 9.2.2.3.1 Junction-to-Ambiant Thermal Impedance (ƟJA)
        4. 9.2.2.4 Motor Current Trip Point
        5. 9.2.2.5 Sense Resistor Selection
        6. 9.2.2.6 Drive Current
      3. 9.2.3 Pulse-Width Modulating
        1. 9.2.3.1 Pulse-Width Modulating ENABLE
        2. 9.2.3.2 Pulse-Width Modulating PHASE
      4. 9.2.4 Application Curves
    3. 9.3 Parallel Configuration
      1. 9.3.1 Parallel Connections
      2. 9.3.2 Non – Parallel Connections
      3. 9.3.3 Wiring nFAULT as Wired OR
      4. 9.3.4 Electrical Considerations
        1. 9.3.4.1 Device Spacing
        2. 9.3.4.2 Recirculation Current Handling
        3. 9.3.4.3 Sense Resistor Selection
        4. 9.3.4.4 Maximum System Current
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-22837F75-F513-4EDA-BC3A-FBA927741A0E-low.gifFigure 5-1 DRV8800 RTY Package16-Pin WQFNTop View
GUID-E0325A66-225F-488A-9379-D15404CBF26F-low.gifFigure 5-2 DRV8801 RTY Package16-Pin WQFNTop View
GUID-D582FC34-1A42-4839-9C45-376A4238F511-low.gifFigure 5-3 DRV8800 PWP Package16-Pin HTSSOPTop View
GUID-49AEB84C-1567-4E8F-8630-8475A0068906-low.gifFigure 5-4 DRV8801 PWP Package16-Pin HTSSOPTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME DRV8800 DRV8801
WQFN HTSSOP WQFN HTSSOP
CP1 10 11 10 11 P Charge pump switching node. Connect a 0.1-μF X7R ceramic capacitor rated for VBB between CP1 and CP2.
CP2 11 12 11 12 P Charge pump switching node. Connect a 0.1-μF X7R ceramic capacitor rated for VBB between CP1 and CP2.
ENABLE 4 6 4 6 I Enable logic input. Set high to enable the H-bridge.
GND 2,12 4, 13 2, 12 4, 13 P Device ground
MODE 16 2 — — I Mode logic input
MODE 1 — — 16 2 I Mode logic input
MODE 2 — — 5 16 I Mode 2 logic input
NC 5 16 — — NC No connect
nFAULT 15 1 15 1 OD Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP 3 5 3 5 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor.
OUT+ 6 7 6 7 O DMOS H-bridge output. Connect to motor terminal.
OUT- 9 10 9 10 O DMOS H-bridge output. Connect to motor terminal.
PHASE 1 3 1 3 I WQFN Package: Phase logic input for direction control.
HTSSOP Package: Phase logic input. Controls the direction of the H-bridge.
SENSE 7 8 7 8 O (DRV8800)
IO (DRV8801)		 Sense Power Return
VBB 8 9 8 9 P Driver supply voltage. Bypass to GND with 0.1-μF ceramic capacitors plus a bulk capacitor rated for VBB.
VCP 13 14 13 14 P Charge pump reservoir capacitor pin. Connect a X7R, 0.1-μF, 16-V ceramic capacitor to VBB.
VREG 14 15 — — P Regulated voltage.
VPROPI — — 14 15 O Voltage output proportional to winding current.
PowerPAD — — — — — Exposed pad for thermal dissipation. Connect to ground.