JAJSLS6D June 2014 – November 2020 DRV8801A-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLIES (VBB) | |||||||
VBB | VBB operating supply voltage | 6.5 | 36 | V | |||
IBB | VBB operating supply current | ƒPWM < 50 kHz | 6 | mA | |||
Charge pump on, Outputs disabled | 3.2 | ||||||
IBB(Q) | VBB sleep-mode supply current | nSLEEP = 0, TJ = 25°C | 10 | μA | |||
CONTROL INPUTS (PHASE, ENABLE, MODE1, MODE2, nSLEEP) | |||||||
VIL | Input logic low voltage | PHASE, ENABLE MODE1, MODE2 | 0.8 | V | |||
VIH | Input logic high voltage | 2 | |||||
IIL | Input logic low current | PHASE, MODE1, MODE2 | VI = 0.8 V | –20 | ≤ –2 | 20 | µA |
IIH | Input logic high current | VI = 2 V | < 1 | 20 | |||
IIL | Input logic low current | ENABLE | VI = 0.8 V | 16 | 40 | μA | |
IIH | Input logic high current | VI = 2 V | 40 | 100 | |||
VIL | Input logic low voltage | nSLEEP | 0.8 | V | |||
VIH | Input logic high voltage | 2.7 | |||||
IIL | Input logic low current | VI = 0.8 V | < 1 | 10 | μA | ||
IIH | Input logic high current | VI = 2 V | 27 | 50 | |||
CONTROL OUTPUTS (nFAULT) | |||||||
VOL | Output logic low voltage | IO = 1 mA | 0.4 | V | |||
DMOS DRIVERS (OUTA, OUTB, SENSE, VPROPI) | |||||||
rDS(on) | Output ON resistance | Source driver, IO = –2.8 A, TJ = 25°C , VBB = 6.5 to 36 V | 0.48 | Ω | |||
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 8 to 36 V | 0.74 | 0.85 | |||||
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 6.5 to 8 V | 0.74 | 0.9 | |||||
Sink driver, IO = 2.8 A, TJ = 25°C, VBB = 6.5 to 36 V | 0.35 | ||||||
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 8 to 36 V | 0.52 | 0.7 | |||||
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 6.5 to 8 V | 0.52 | 0.75 | |||||
V(TRIP) | SENSE trip voltage | R(SENSE) between SENSE and GND | 450 | 500 | 550 | mV | |
Vf | Body diode forward voltage | Source diode, If = –2.8 A | 1.4 | V | |||
Sink diode, If = 2.8 A | 1.4 | ||||||
tpd | Propagation delay time | Input edge to source or sink ON | 600 | ns | |||
Input edge to source or sink OFF | 100 | ||||||
tCOD | Crossover delay | 500 | ns | ||||
GD(a) | Differential amplifier gain | VBB = 8 to 36 V; SENSE = 0.1 to 0.4 V | 4.8 | 5 | 5.2 | V/V | |
VBB = 6.5 to 8 V; SENSE = 0.1 to 0.3 V | 4.8 | 5.2 | V/V | ||||
PROTECTION CIRCUITS | |||||||
VUV | UVLO threshold | VBB increasing | 5.5 | 6.4 | V | ||
VBB decreasing | 5.7 | ||||||
UVLO hysteresis | 500 | 850 | mV | ||||
I(OCP) | Overcurrent protection trip level | VBB = 8 to 36 V | 3 | A | |||
VBB = 6.5 to 8 V | 2.8 | A | |||||
t(DEG) | Overcurrent deglitch time | 3 | µs | ||||
t(OCP) | Overcurrent retry time | 0.5 | 1.2 | 3 | ms | ||
T(OTW) | Thermal warning temperature | Die temperature TJ | 160 | °C | |||
Thys(OTW) | Thermal warning hysteresis | Die temperature TJ | 15 | °C | |||
T(OTS) | Thermal shutdown temperature | Die temperature TJ | 175 | °C | |||
Thys(OTS) | Thermal shutdown hysteresis | Die temperature TJ | 15 | °C |