JAJSI17D November   2013  – October 2019 DRV8850

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supervisor
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Sensing – VPROPI
      4. 7.3.4 Slew-Rate Control
      5. 7.3.5 Dead Time
      6. 7.3.6 Propagation Delay
      7. 7.3.7 Power Supplies and Input Pins
      8. 7.3.8 LDO Voltage Regulator
      9. 7.3.9 Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Thermal Shutdown (TSD)
        3. 7.3.9.3 Undervoltage Lockout (UVLO)
        4. 7.3.9.4 Overvoltage Lockout (OVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGY Package
24-Pin VQFN With Exposed Thermal Pad
Top View
DRV8850 po_QFN_SLVSCC0.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
POWER AND GROUND
GND 1, 12, 13, 24, Thermal pad — Device ground
LDOOUT 15 — LDO regulator output Bypass to GND with a 2.2-μF 6.3-V ceramic capacitor
VCC 18, 19, 20 — Device supply Bypass to GND with 0.1-μF and 10-μF 6.3-V ceramic capacitors
VCP 17 — Charge pump Connect a 0.1-μF 6.3-V ceramic capacitor to VCC
CONTROL
IN1H 5 I Input 1 HS FET enable Active high enables HS FET for output 1
Internal pulldown resistor
IN1L 6 I Input 1 LS FET enable Active high enables LS FET for output 1
Internal pulldown resistor
IN2H 7 I Input 2 HS FET enable Active high enables HS FET for output 2
Internal pulldown resistor
IN2L 8 I Input 2 LS FET enable Active high enables LS FET for output 2
Internal pulldown resistor
LDOEN 10 I LDO regulator enable Logic low disables LDO regulator
Logic high enables LDO regulator
Internal pulldown resistor
LDOFB 14 I LDO regulator feedback Resistor divider from LDOOUT sets LDO output voltage
May be connected to LDOIN to enable LDO
nSLEEP 9 I Sleep mode input Logic low puts device in low-power sleep mode
Logic high for typical operation
Internal pulldown resistor
SR 11 IO Slew rate control Resistor to ground sets output slew rate
OUTPUT
OUT1 2, 3, 4 O Output 1 Connect to motor winding
OUT2 21, 22, 23 O Output 2
VPROPI 16 O Current sense output Output current is proportional to H-bridge current. 1 kΩ, 1% resistor to GND for 2-A maximum current with VCC at 2 V. See Equation 1 if more current is required
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input or output