JAJSCP6 November   2016 DRV8872-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Sleep Mode
      3. 7.3.3 Current Regulation
      4. 7.3.4 Dead Time
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.5.2 Overcurrent Protection (OCP)
        3. 7.3.5.3 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM With Current Regulation
      2. 7.4.2 PWM Without Current Regulation
      3. 7.4.3 Static Inputs With Current Regulation
      4. 7.4.4 VM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
        3. 8.2.2.3 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
      1. 10.4.1 Heatsinking
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The DRV8872-Q1 device is an optimized 8-pin device for driving brushed DC motors with 6.8 to 45 V and up to 3.6-A peak current. The integrated current regulation restricts motor current to a predefined maximum. Two logic inputs control the H-bridge driver, which consists of four N-channel MOSFETs that have a typical Rds(on) of 565 mΩ (including one high-side and one low-side FET). A single power input, VM, serves as both device power and the motor winding bias voltage. The integrated charge pump of the device boosts VM internally and fully enhances the high-side FETs. Motor speed can be controlled with pulse-width modulation, at frequencies between 0 to 200 kHz. The device has an integrated sleep mode that is entered by bringing both inputs low. An assortment of protection features prevent the device from being damaged if a system fault occurs.

7.2 Functional Block Diagram

DRV8872-Q1 fbd_slis175.gif

7.3 Feature Description

7.3.1 Bridge Control

The DRV8872-Q1 output consists of four N-channel MOSFETs that are designed to drive high current. These MOSFETs are controlled by the two logic inputs IN1 and IN2, according to Table 1.

Table 1. H-Bridge Control

IN1 IN2 OUT1 OUT2 DESCRIPTION
0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after 1 ms)
0 1 L H Reverse (current OUT2 → OUT1)
1 0 H L Forward (current OUT1 → OUT2)
1 1 L L Brake; low-side slow decay

The inputs can be set to static voltages for 100% duty-cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of its max RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. The input pins can be powered before VM is applied.

DRV8872-Q1 bridge_control_lvscy8.gif Figure 4. H-Bridge Current Paths

7.3.2 Sleep Mode

When IN1 and IN2 are both low for time tSLEEP (typically 1 ms), the DRV8872-Q1 device enters a low-power sleep mode, where the outputs remain High-Z and the device uses IVMSLEEP (microamps) of current. If the device is powered up while both inputs are low, sleep mode is immediately entered. After IN1 or IN2 are high for at least 5 µs, the device is operational 50 µs (tON) later.

7.3.3 Current Regulation

The DRV8872-Q1 device limits the output current based on the resistance of an external sense resistor on pin ISEN, according to Equation 1.

Equation 1. DRV8872-Q1 eq_I_TRIP_lvscz0.gif

For example, if RISEN = 0.16 Ω, the DRV8872-Q1 device limits motor current to 2.2 A no matter how much load torque is applied. For guidelines on selecting a sense resistor, see the Sense Resistor section.

When ITRIP has been reached, the device enforces slow current decay by enabling both low-side FETs, and it does this for time tOFF (typically 25 µs).

DRV8872-Q1 current_reg_lvscy9.gif Figure 5. Current Regulation Time Periods

After tOFF has elapsed, the output is re-enabled according to the two inputs INx. The drive time (tDRIVE) until reaching another ITRIP event heavily depends on the VM voltage, the back-EMF of the motor, and the inductance of the motor.

7.3.4 Dead Time

When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. tDEAD is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage will depend on the direction of current. If current is leaving the pin, the voltage is a diode drop below ground. If current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET.

DRV8872-Q1 prop_delay_lvscy9.gif Figure 6. Propagation Delay Time

7.3.5 Protection Circuits

The DRV8872-Q1 device is fully protected against VM undervoltage, overcurrent, and overtemperature events. When the device is in a protected state, nFAULT is driven low. When the fault condition is removed, nFAULT becomes a high-impedance state.

7.3.5.1 VM Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the undervoltage-lockout threshold voltage, all FETs in the H-bridge are disabled. Operation resumes when VM rises above the UVLO threshold.

7.3.5.2 Overcurrent Protection (OCP)

If the output current exceeds the OCP threshold IOCP for longer than tOCP, all FETs in the H-bridge are disabled for a duration of tRETRY. After that, the H-bridge re-enables according to the state of the INx pins. If the overcurrent fault is still present, the cycle repeats; otherwise normal device operation resumes.

7.3.5.3 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge is disabled. After the die temperature has fallen to a safe level, operation automatically resumes.

Table 2. Protection Functionality

FAULT CONDITION H-BRIDGE BECOMES NFAULT BECOMES RECOVERY
VM undervoltage lockout (UVLO) VM < VUVLO Disabled Low VM > VUVLO
Overcurrent (OCP) IOUT > IOCP Disabled Low tRETRY
Thermal shutdown (TSD) TJ > 150°C Disabled Low TJ < TSD - T HYS

7.4 Device Functional Modes

The DRV8872-Q1 device can be used in multiple ways to drive a brushed DC motor.

7.4.1 PWM With Current Regulation

This scheme uses all of the capabilities of the device. The ITRIP current is set above the normal operating current, and high enough to achieve an adequate spin-up time, but low enough to constrain current to a desired level. Motor speed is controlled by the duty cycle of one of the inputs, while the other input is static. Brake and slow decay is typically used during the off-time.

7.4.2 PWM Without Current Regulation

If current regulation is not needed, the ISEN pin should be directly connected to the PCB ground plane. This mode provides the highest possible peak current: up to 3.6 A for a few hundred milliseconds (depending on PCB characteristics and the ambient temperature). If current exceeds 3.6 A, the device might reach overcurrent protection (OCP) or over-temperature shutdown (TSD). If that occurs, the device disables and protects itself for about 3 ms (tRETRY) and then resumes normal operation.

7.4.3 Static Inputs With Current Regulation

The IN1 and IN2 pins can be set high and low for 100% duty cycle drive, and ITRIP can be used to control the current, speed, and torque capability of the motor.

7.4.4 VM Control

In some systems, varying VM as a means of changing motor speed is desirable. See the Motor Voltage section for more information.