JAJSCW7D January   2016  – November 2018 DRV8884

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      マイクロステッピング電流の波形
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Indexer Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Stepper Motor Driver Current Ratings
        1. 8.3.1.1 Peak Current Rating
        2. 8.3.1.2 RMS Current Rating
        3. 8.3.1.3 Full-Scale Current Rating
      2. 8.3.2  PWM Motor Drivers
      3. 8.3.3  Microstepping Indexer
      4. 8.3.4  Current Regulation
      5. 8.3.5  Controlling RREF With an MCU DAC
      6. 8.3.6  Decay Modes
        1. 8.3.6.1 Mode 1: Slow Decay for Increasing and Decreasing Current
        2. 8.3.6.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 8.3.6.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
      7. 8.3.7  Blanking Time
      8. 8.3.8  Charge Pump
      9. 8.3.9  LDO Voltage Regulator
      10. 8.3.10 Logic and Multi-Level Pin Diagrams
      11. 8.3.11 Protection Circuits
        1. 8.3.11.1 VM UVLO
        2. 8.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 8.3.11.3 Overcurrent Protection (OCP)
        4. 8.3.11.4 Thermal Shutdown (TSD)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stepper Motor Speed
        2. 9.2.2.2 Current Regulation
        3. 9.2.2.3 Decay Modes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP PowerPAD™ Package
24-Pin HTSSOP
Top View
RHR Package
28-Pin WQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
HTSSOP WQFN
AOUT1 5 3 O Winding A output. Connect to stepper motor winding.
AOUT2 7 5
AVDD 13 12 PWR Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
BOUT1 10 8 O Winding B output. Connect to stepper motor winding.
BOUT2 8 6
CPH 2 28 PWR Charge pump switching node. Connect a X5R or X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
CPL 1 27
DECAY 24 25 I Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode can be adjusted during operation.
DIR 20 21 I Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
DVDD 14 13 PWR Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
ENABLE 18 19 I Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor.
GND 12 10 PWR Device ground. Connect to system ground.
M0 21 22 I Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor.
M1 22 23
NC — 11 — No connect. No internal connection
14
15
26
PGND 6 4 PWR Power ground. Connect to system ground.
9 7
RREF 16 17 I Current-limit analog input. Connect a resistor to ground to set full-scale regulation current.
STEP 19 20 I Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
TRQ 23 24 I Current-scaling control. Scales the output current; tri-level pin.
VCP 3 1 PWR Charge pump output. Connect a X5R or X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM 4 2 PWR Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
11 9
nFAULT 15 16 OD Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP 17 18 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor.
(1) I = input, O = output, PWR = power, OD = open-drain