DS125DF410は4チャネルのリタイマで、信号コンディショニングが内蔵されています。このデバイスには、完全なアダプティブ連続時間リニア・イコライザ(CTLE)、自己較正型5タップ決定フィードバック・イコライザ(DFE)、クロックおよびデータ回復(CDR)、送信ディエンファシス(DE)ドライバが含まれており、長距離で損失が多く、クロストークを受ける高速シリアル・リンク上でデータ伝送を可能にし、BER < 1×10-15を実現できます。
各チャネルは9.8~12.5Gbpsのデータ・レート、および関連するサブレート(2、4、8で除算)に独立にロックでき、各種の通信プロトコルをサポートします。25MHzの水晶発振器のクロックを使用して、CDRのロック・プロセスが高速化されます。このクロックはPLLのトレーニングには使用されず、シリアル・データと同期している必要はありません。
プログラム可能な設定は、SMBus (I2C)インターフェイスを使用して適用することも、外部のEEPROMでロードすることもできます。オンチップのアイ・モニタとPRBSジェネレータにより、高速のシリアル・データをリアルタイムで測定でき、システムの調整や現場でのチューニングに使用できます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
DS125DF410 | WQFN (48) | 7.00mm×7.00mm |
Changes from G Revision (March 2015) to H Revision
Changes from F Revision (January 2015) to G Revision
Changes from E Revision (May 2013) to F Revision
PIN | TYPE
I/O (1) |
DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
HIGH-SPEED DIFFERENTIAL I/O | |||
RXP0
RXN0 |
1
2 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. |
RXP1
RXN1 |
4
5 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. |
RXP2
RXN2 |
8
9 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. |
RXP3
RXN3 |
11
12 |
I, CML | Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. |
TXP0
TXN0 |
36
35 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. |
TXP1
TXN1 |
33
32 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. |
TXP2
TXN2 |
29
28 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. |
TXP3
TXN3 |
26
25 |
O, CML | Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. |
LOOP FILTER CONNECTION PINS | |||
LPF_CP_0
LPF_REF_0 |
47
48 |
I/O, analog | Loop filter connection
Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0 |
LPF_CP_1
LPF_REF_1 |
38
37 |
I/O, analog | Loop filter connection
Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1 |
LPF_CP_2
LPF_REF_2 |
23
24 |
I/O, analog | Loop filter connection
Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2 |
LPF_CP_3
LPF_REF_3 |
14
13 |
I/O, analog | Loop filter connection
Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3 |
REFERENCE CLOCK I/O | |||
REFCLK_IN | 19 | I, 2.5 V analog | Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator
No stringent phase noise requirement |
REFCLK_OUT | 42 | O, 2.5 V analog | Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS125DF410s on a board |
LOCK INDICATOR PINS | |||
LOCK0
LOCK1 LOCK2 LOCK3 |
45
40 21 16 |
O, 2.5 V LVCMOS | Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel.
Note that these pins are shared with SMBus address strap input functions read at startup. |
SMBus MASTER MODE PINS | |||
ALL_DONE | 41 | O, 2.5 V LVCMOS | Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been completed. |
READ_EN | 44 | I, 2.5 V LVCMOS | Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN pin must be tied low when in SMBus slave mode. |
INTERRUPT OUTPUT | |||
INT | 43 | O, 3.3 V LVCMOS,
Open Drain |
Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, or CDR unlock.
External 2kΩ to 5kΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
SERIAL MANAGEMENT BUS (SMBus) INTERFACE | |||
EN_SMB | 20 | I, 2.5 V analog | Input is 2.5 V, selects SMBus master mode or SMBus slave mode.
EN_SMB = High for slave mode EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 4 |
SDA | 18 | I/O, 3.3 V LVCMOS,
Open Drain |
Data Input / Open Drain Output
External 2kΩ to 5kΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
SDC | 17 | I/O, 3.3 V LVCMOS,
Open Drain |
Clock Input / Open Drain Clock Output
External 2kΩ to 5kΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. |
ADDR_0
ADDR_1 ADDR_2 ADDR_3 |
45
40 21 16 |
I, 2.5 V LVCMOS | Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.
These pins are strap inputs. Their state is read on power-up to set the SMBus address in SMBus control mode. High = 1kΩ to VDD, Low = 1kΩ to GND Note that these pins are shared with the lock indicator functions. See Table 1 |
POWER | |||
VDD | 3, 6, 7,
10, 15, 46 |
Power | VDD = 2.5 V ± 5% |
GND | 22, 27,
30, 31, 34, 39 |
Power | Ground reference. |
DAP | PAD | Power | Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package. |