JAJSHS2 August   2019 DS160PR410

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIE x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
XTRX Receive-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 8 GHz. -45 dB
Transmitter
VTX-AC-CM-PP Tx AC Peak-to-Peak Common Mode Voltage Measured with lowest EQ, VOD = L2; PRBS-7, 16 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30Khz-500Mhz 50 mVpp
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC = |VOUTn+ + VOUTn–|/2, Measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle 0 100 mV
VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common Mode Voltage between VOUTn+ and VOUTn– during L0 Measured by taking the absolute difference of VOUTn+ and VOUTn– during PCIe state L0 0 10 mV
VTX-IDLE-DIFF-AC-p AC Electrical Idle Differential Output Voltage Measured by taking the absolute difference of VOUTn+ and VOUTn– during Electrical Idle, Measured with a band-pass filter consisting of two first-order filters. The High-Pass and Low-Pass –3-dB bandwidths are 10 kHz and 1.25 GHz, respectively - zero at input 0 10 mV
VTX-IDLE-DIFF-DC DC Electrical Idle Differential Output Voltage Measured by taking the absolute difference of VOUTn+ and VOUTn– during Electrical Idle, Measured with a first-order Low-Pass Filter with –3-dB bandwidth of 10 kHz 0 5 mV
VTX-RCV-DETECT Amount of Voltage change allowed during Receiver Detection Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output 0 600 mV
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 8 GHz. -45 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a channel Measured by observing propagation delay during either Low-to-High or High-to-Low transition 100 130 ps
LTX-SKEW Lane-to-Lane Output Skew Measured between any two lanes within a single transmitter 14 20 ps
TTX-DJ-ADD Added Deterministic Jitter  Difference between measurement through redriver and baseline setup with 16Gbps PRBS15 with minimum input and output channels with minimum EQ setting. 2.5 5 ps
TTX-RJ-ADD Additive Random Jitter Difference between measurement through redriver and baseline setup with 16Gbps PRBS15 with minimum input and output channels with minimum EQ setting. 160 200 fs RMS
DCGAINVAR,max Maximum DC gain variation VOD=L2, GAIN=L2, min EQ setting -1.5 1.5 dB
ACGAINVAR,max Maximum EQ boost variation VOD=L2, GAIN=L2, max EQ setting, at 8Ghz -3.0 3.0 dB
LINEARITYDC Input amplitude linear range. The maximum VID for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin. Measured with the highest wide-band gain setting (VOD = L2,). Measured with minimal input channel and minimum EQ using 128T pattern at 2.5 Gbps. 800 mVpp
LINEARITYAC Input amplitude linear range. The maximum VID for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin. Measured with the highest wide-band gain setting (VOD = L2,). Measured with minimal input channel and minimum EQ using 1T pattern at 16 Gbps 750 mVpp
JITTERINTRINSIC-RJ Redriver intrinsic additive Random Jitter (RMS) Difference between measurement through redriver and baseline setup with 8Ghz clock signals, lowest EQ 160 190 fs
JITTERINTRINSIC-DJ Redriver intrinsic additive Deterministic Jitter Difference between measurement through redriver and baseline setup with 8Ghz clock signals, lowest EQ 0.4 1.2 ps
JITTERINTRINSIC-TOTAL Redriver intrinsic additive Total Jitter Difference between measurement through redriver and baseline setup with 8Ghz clock signals, lowest EQ 2.5 3.5 ps