JAJSI41B February   2017  – October 2019 DS250DF210

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Precursor, and Postcursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Backplane and Mid-Plane Applications
      4. 9.2.4 Design Requirements
      5. 9.2.5 Detailed Design Procedure
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Differential Driver With FIR Filter

The DS250DF210 output driver has a three-tap finite impulse response (FIR) filter which allows for precursor and postcursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted sum of three consecutive retimed bits as shown in the following diagram. C[0] can take on values in the range [-31, +31]. C[-1] and C[+1] can take on values in the range [-15, 15].

DS250DF210 bd_fir.gifFigure 7. FIR Filter Functional Model

When using the FIR filter, it is important to abide by the following general rules:

  • |C[-1]| + |C[0]| + |C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31
  • sgn(C[-1]) = sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the precursor or postcursor tap must be different from main-cursor tap to realize boost effect
  • sgn(C[-1]) = sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the precursor or postcursor tap must be equal to the main-cursor tap to realize attenuation effect

The FIR filter is used to predistort the transmitted waveform in order to compensate for frequency-dependant loss in the output channel. The most common way of predistorting the signal is to accentuate the transitions and de-emphasize the non-transitions. The bit before a transition is accentuated via the precursor tap, and the bit after the transition is accentuated through the postcursor tap. The figures below give a conceptual illustration of how the FIR filter affects the output waveform. The following characteristics can be derived from the example waveforms.

  • VODpk-pk= v7 - v8
  • VODlow-frequency = v2 - v5
  • RpredB = 20 * log10 (v3 ⁄v2 )
  • RpstdB = 20 * log10 (v1 ⁄v2 )
DS250DF210 fir_wfm_postonly.gifFigure 8. Conceptual FIR Waveform With Postcursor Only
DS250DF210 fir_wfm_preonly.gifFigure 9. Conceptual FIR Waveform With Precursor Only
DS250DF210 fir_wfm_full.gifFigure 10. Conceptual FIR Waveform With Both Precursor and Postcursor