JAJSI43C December   2015  – October 2019 DS250DF810

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  AC-Coupled Receiver and Transmitter
      3. 8.3.3  Signal Detect
      4. 8.3.4  Continuous Time Linear Equalizer (CTLE)
      5. 8.3.5  Variable Gain Amplifier (VGA)
      6. 8.3.6  Cross-Point Switch
      7. 8.3.7  Decision Feedback Equalizer (DFE)
      8. 8.3.8  Clock and Data Recovery (CDR)
      9. 8.3.9  Calibration Clock
      10. 8.3.10 Differential Driver with FIR Filter
      11. 8.3.11 Setting the Output VOD
      12. 8.3.12 Output Driver Polarity Inversion
      13. 8.3.13 Debug Features
        1. 8.3.13.1 Pattern Generator
        2. 8.3.13.2 Pattern Checker
        3. 8.3.13.3 Eye Opening Monitor
      14. 8.3.14 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Applications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.11 Setting the Output VOD

The output differential voltage (VOD) of the driver is controlled by manipulating the FIR tap settings. The main cursor tap is the primary knob for amplitude adjustment. The pre and post cursor FIR tap settings can then be adjusted to provide equalization. To maintain a constant peak-to-peak VOD, the user should adjust the main cursor tap value relative to the pre/post tap changes so as to maintain a constant absolute sum of the FIR tap values. The table below shows various settings for VOD settings ranging from 205 mVpp to 1225 mVpp (typical). Note that the output peak-to-peak amplitude is a function of the sum of the absolute values of the taps, whereas the low-frequency amplitude is purely a function of the main-cursor value.

Table 2. Typical VOD and FIR Values

FIR SETTINGS Peak-to Peak VOD(V) RPRE(dB) RPST(dB)
PRE-CURSOR:
REG_0x3E[6:0]		 MAIN-CURSOR:
REG_0x3D[6:0]		 POST-CURSOR:
REG_0x3F[6:0]
0 0 0 0.205 NA NA
0 +1 0 0.260 NA NA
0 +2 0 0.305 NA NA
0 +3 0 0.355 NA NA
0 +4 0 0.395 NA NA
0 +5 0 0.440 NA NA
0 +6 0 0.490 NA NA
0 +7 0 0.525 NA NA
0 +8 0 0.565 NA NA
0 +9 0 0.610 NA NA
0 +10 0 0.650 NA NA
0 +11 0 0.685 NA NA
0 +12 0 0.720 NA NA
0 +13 0 0.760 NA NA
0 +14 0 0.790 NA NA
0 +15 0 0.825 NA NA
0 +16 0 0.860 NA NA
0 +17 0 0.890 NA NA
0 +18 0 0.925 NA NA
0 +19 0 0.960 NA NA
0 +20 0 0.985 NA NA
0 +21 0 1.010 NA NA
0 +22 0 1.040 NA NA
0 +23 0 1.075 NA NA
0 +24 0 1.095 NA NA
0 +25 0 1.125 NA NA
0 +26 0 1.150 NA NA
0 +27 0 1.165 NA NA
0 +28 0 1.190 NA NA
0 +29 0 1.205 NA NA
0 +30 0 1.220 NA NA
0 +31 0 1.225 NA NA
0 +18 -1 0.960 NA 2.1
0 +17 -2 0.960 NA 2.5
0 +16 -3 0.960 NA 3.1
0 +15 -4 0.960 NA 3.8
0 +14 -5 0.960 NA 4.7
0 +13 -6 0.960 NA 5.8
0 +12 -7 0.960 NA 7.2
0 +11 -8 0.960 NA 9.0
0 +10 -9 0.960 NA 11.6
-1 18 0 0.960 1.0 NA
-2 17 0 0.960 1.6 NA
-3 16 0 0.960 2.4 NA
-4 15 0 0.960 3.3 NA
0 26 -1 1.165 NA 1.1
0 25 -2 1.165 NA 1.3
0 24 -3 1.165 NA 1.8
0 23 -4 1.165 NA 2.2
0 22 -5 1.165 NA 2.7
0 21 -6 1.165 NA 3.3
0 20 -7 1.165 NA 3.9
0 19 -8 1.165 NA 4.7
0 18 -9 1.165 NA 5.7
0 17 -10 1.165 NA 6.9
0 16 -11 1.165 NA 8.4
0 15 -12 1.165 NA 10.1
-1 26 0 1.165 0.7 NA
-2 25 0 1.165 1.2 NA
-3 24 0 1.165 1.5 NA
-4 23 0 1.165 2.0 NA
-5 22 0 1.165 2.6 NA
-6 21 0 1.165 3.2 NA
-7 20 0 1.165 4.0 NA

The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The DS250DF810 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre- or post-cursor. The figures below give general recommendations for pre- and post-cursor for different channel loss conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner transmitter and the DS250DF810 receiver.

DS250DF810 FIR_setting_IL_15dB.gifFigure 11. Guideline for link partner FIR settings when IL ≤ 15dB
DS250DF810 FIR_setting_IL_25dB.gifFigure 12. Guideline for link partner FIR settings when IL ≤ 25dB
DS250DF810 FIR_setting_IL_35dB.gifFigure 13. Guideline for link partner FIR settings when IL ≤ 35dB