JAJSI43C December   2015  – October 2019 DS250DF810

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  AC-Coupled Receiver and Transmitter
      3. 8.3.3  Signal Detect
      4. 8.3.4  Continuous Time Linear Equalizer (CTLE)
      5. 8.3.5  Variable Gain Amplifier (VGA)
      6. 8.3.6  Cross-Point Switch
      7. 8.3.7  Decision Feedback Equalizer (DFE)
      8. 8.3.8  Clock and Data Recovery (CDR)
      9. 8.3.9  Calibration Clock
      10. 8.3.10 Differential Driver with FIR Filter
      11. 8.3.11 Setting the Output VOD
      12. 8.3.12 Output Driver Polarity Inversion
      13. 8.3.13 Debug Features
        1. 8.3.13.1 Pattern Generator
        2. 8.3.13.2 Pattern Checker
        3. 8.3.13.3 Eye Opening Monitor
      14. 8.3.14 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Applications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

135-pin fcBGA, 0.8mm BGA pin pitch
Top View
DS250DF810 pin_map.gif

Pin Functions

PIN TYPE INTERNAL
PULL-UP/
PULL-DOWN		 DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/Os
RX0P C15 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX0N B15 Input None
RX1P B13 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX1N A13 Input None
RX2P B11 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX2N A11 Input None
RX3P B9 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX3N A9 Input None
RX4P B7 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX4N A7 Input None
RX5P B5 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX5N A5 Input None
RX6P B3 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX6N A3 Input None
RX7P C1 Input None Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled on-chip with physical 220nF capacitors.
RX7N B1 Input None
TX0P G15 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX0N H15 Output None
TX1P H13 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX1N J13 Output None
TX2P H11 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX2N J11 Output None
TX3P H9 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX3N J9 Output None
TX4P H7 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX4N J7 Output None
TX5P H5 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX5N J5 Output None
TX6P H3 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX6N J3 Output None
TX7P G1 Output None Inverting and non-inverting 50Ω driver outputs. These outputs are AC coupled on-chip with physical 220nF capacitors.
TX7N H1 Output None
CALIBRATION CLOCK PINS
CAL_CLK_IN E1 Input, 2.5V CMOS None 25 MHz (±100 PPM) 2.5 V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. Used to calibrate VCO frequency range. This clock is not used to recover data.
CAL_CLK_OUT E15 Output, 2.5V CMOS None 2.5 V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a daisy-chained fashion.
SYSTEM MANAGEMENT BUS (SMBUS) PINS
ADDR0 D13 Input, 4-level None 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include:
0: 1 kΩ to GND
R: 10 kΩ to GND
F: Float
1: 1 kΩ to VDD
ADDR1 E13 Input, 4-level None
EN_SMB E3 Input, 4-level None Four-level 2.5 V input used to select between SMBus master mode (float) and SMBus slave mode (high). The four defined levels are:
0: 1 kΩ to GND - RESERVED
R: 10 kΩ to GND - RESERVED, TI test mode
F: Float - SMBus Master Mode
1: 1 kΩ to VDD - SMBus Slave Mode
SDA E12 I/O, 3.3V LVCMOS, Open Drain None SMBus data input / open drain output. External 2 kΩ to 5 kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3 V LVCMOS tolerant.
SDC F12 I/O, 3.3V LVCMOS, Open Drain None SMBus clock input / open drain clock output. External 2 kΩ to 5 kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3 V LVCMOS tolerant.
SMBUS MASTER MODE PINS
READ_EN_N F13 Input, 3.3V LVCMOS weak pull-up SMBus Master Mode (EN_SMB=Float): When asserted low, initiates the SMBus master mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. This pin is 3.3 V tolerant.
SMBus Slave Mode (EN_SMB=1): When asserted low, this causes the device to be held in reset (I2C state machine reset and register reset). This pin should be pulled high or left floating for normal operation in SMBus Slave Mode. This pin is 3.3 V tolerant.
ALL_DONE_N D3 Output, LVCMOS None Indicates the completion of a valid EEPROM register load operation when in SMBus Master Mode (EN_SMB=Float):
High = External EEPROM load failed or incomplete
Low = External EEPROM load successful and complete
When in SMBus slave mode (EN_SMB=1), this output will be high-z until READ_EN_N is driven low, at which point ALL_DONE_N will be driven low.
MISCELLANEOUS PINS
INT_N F3 Output, LVCMOS, Open-Drain None Open-drain 3.3 V tolerant active-low interrupt output. It pulls low when an interrupt occurs. The events which trigger an interrupt are programmable through SMBus registers. This pin can be connected in a wired-OR fashion with other device's interrupt pin. A single pull-up resistor in the 2 kΩ to 5 kΩ range is adequate for the entire INT_N net.
TEST0 E2 Input, LVCMOS weak pull-up Reserved TI test pin. During normal (non-test-mode) operation, these pins are configured as inputs and therefore are not affected by the presence of a signal. These pins may be left floating, tied to GND, or connected to a 2.5V (max) output.
TEST1 E14 Input, LVCMOS weak pull-up
TEST4 F4 Input, LVCMOS None Reserved TI test pin. During normal (non-test-mode) operation, this pin is configured as an input and therefore is not affected by the presence of a signal. This pin should be tied to GND or left floating to support both the Repeater and Retimer device.
TEST5 E4 Input, LVCMOS None Reserved TI test pin. During normal (non-test-mode) operation, this pin is configured as an input and therefore is not affected by the presence of a signal. This pin may be left floating, tied to GND, or connected to a 2.5V (max) output.
TEST6 D4 Input, LVCMOS None
TEST7 D12 Input, LVCMOS None
POWER
VDD D6, D8, D10, E5, E6, E7, E8, E9, E10, F6, F8, F10 Power None Power supply, VDD = 2.5 V ±5%. TI recommends connecting at least six de-coupling capacitors between the Retimer’s VDD plane and GND as close to the Retimer as possible. For example, four 0.1 μF capacitors and two 1 μF capacitors directly beneath the device or as close to the VDD pins as possible.
The VDD pins on this device should be connected through a low-resistance path to the board VDD plane.
GND A1, A2, A4, A6, A8, A10, A12, A14, A15, B2, B4, B6, B8, B10, B12, B14, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, D1, D2, D5, D7, D9, D11, D14, D15, E11, F1, F2, F5, F7, F9, F11, F14, F15, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, H2, H4, H6, H8, H10, H12, H14, J1, J2, J4, J6, J8, J10, J12, J14, J15 Power None Ground reference. The GND pins on this device should be connected through a low-resistance path to the board GND plane.