JAJSI57B September 2016 – February 2024 DS280DF810
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
For this design example, the following guidelines outlined in Table 7-2 apply.
DESIGN PARAMETER | REQUIREMENT |
---|---|
AC coupling capacitors | Not required. AC coupling capacitors are included in the device package. |
Input channel insertion loss | ≤ 35dB at 25.78125Gbps Nyquist frequency. ≤ 30dB at 28Gbps Nyquist frequency. |
Output channel insertion loss | Egress (ASIC-to-module) direction: Follow CAUI-4 / CEI-25G-VSR host channel requirements (approximately 7dB at 12.9GHz). Ingress (module-to-ASIC) direction: Depends on downstream ASIC and FPGA capabilities. The DS280DF810 has a low-jitter output driver with 3-tap FIR filter for equalizing a portion of the output channel. |
Host ASIC TX launch amplitude | 800mVppd to 1200mVppd |
Hos ASIC TX FIR filter | Depends on channel loss. Refer to Section 6.3.1.9.1. |