JAJSI38C october 2016 – december 2020 DS280MB810
PRODUCTION DATA
Addr [HEX] | Bit | Default [HEX] | Mode | EEPROM | Field | Description |
---|---|---|---|---|---|---|
0x00 | 0x00 | General | ||||
7 | 0 | RW | N | CLK_CORE_DISAB | 1: Disables 10 M core clock. This is the main clock domain for all the state machines. 0: Normal operation | |
6 | 0 | RW | N | CLK_REGS_EN | 1: Force enable the clock to the registers. Normally, the register clock is enabled automatically on a needed basis. 0: Normal operation | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | CLK_REF_DISAB | 1: Disables the 25 MHz CAL_CLK domain. 0: Normal operation | |
3 | 0 | RW | N | RST_CORE | 1: Reset the 10 M core clock domain. This is the main clock domain for all the state machines. 0: Normal operation | |
2 | 0 | RWSC | N | RST_REGS | 1: Reset channel registers to power-up defaults. 0: Normal operation | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RST_CAL_CLK | 1: Resets the 25 MHz reference clock domain. 0: Normal operation | |
0x01 | 0x01 | SIG_DET | ||||
7 | 0 | R | N | SIGDET | Signal detect status. 1: Signal detected at RX inputs. 0: No signal detected at RX inputs. | |
6 | 0 | R | N | SIGDET_ADJACENT | Signal detect status of adjacent channel. "Adjacent," referring to channel N+1 if N is even, or channel N-1 if N is odd. 1: Signal detected at RX inputs of adjacent channel. 0: No signal detected at RX inputs. | |
5 | 0 | R | N | RESERVED | RESERVED | |
4 | 0 | R | N | RESERVED | RESERVED | |
3 | 0 | R | N | RESERVED | RESERVED | |
2 | 0 | R | N | RESERVED | RESERVED | |
1 | 0 | R | N | RESERVED | RESERVED | |
0 | 1 | R | N | RESERVED | RESERVED | |
0x02 | 0x00 | |||||
7 | 0 | R | N | RESERVED | RESERVED | |
6 | 0 | R | N | RESERVED | RESERVED | |
5 | 0 | R | N | RESERVED | RESERVED | |
4 | 0 | R | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x03 | 0x80 | CTLE_BOOST | ||||
7 | 1 | RW | Y | EQ_BW[1] | EQ stage one buffer current (strength) control. Impacts EQ bandwidth. 2'b11 yields highest bandwidth, 2'b00 yields lowest bandwidth. Refer to the Programming Guide for more information. | |
6 | 0 | RW | Y | EQ_BW[0] | ||
5 | 0 | RW | Y | EQ_BST2[2] | EQ boost stage 2 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information. | |
4 | 0 | RW | Y | EQ_BST2[1] | ||
3 | 0 | RW | Y | EQ_BST2[0] | ||
2 | 0 | RW | Y | EQ_BST1[2] | EQ boost stage 1 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information. | |
1 | 0 | RW | Y | EQ_BST1[1] | ||
0 | 0 | RW | Y | EQ_BST1[0] | ||
0x04 | 0x90 | |||||
7 | 1 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | EQ_PD_SD | 1: Power down signal detect | |
0: Normal operation | ||||||
5 | 0 | RW | Y | EQ_HIGH_GAIN | 1: Enable EQ high gain | |
0: Enable EQ low gain | ||||||
4 | 1 | RW | Y | EQ_EN_DC_OFF | RESERVED | |
3 | 0 | RW | Y | EQ_PD_EQ | 1: Power down EQ | |
0: Enable EQ | ||||||
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | Y | BG_SEL_IPP100[2] | CTLE bias programming. BG_SEL_IPP100[1:0] is in Reg_0x0F[5:4]. | |
0 | 0 | RW | Y | EQ_EN_BYPASS | 1: Enable EQ boost stage 1 (BST1) bypass. | |
0: Normal operation, signal travels through boost stage 1 (BST1). | ||||||
0x05 | 0x04 | SIG_DET_CONFIG | ||||
7 | 0 | RW | Y | EQ_SD_PRESET | 1: Force signal detect result to 1. | |
0: Normal operation | ||||||
This bit should not be set if 0x05[6] is also set. | ||||||
6 | 0 | RW | Y | EQ_SD_RESET | 1: Force signal detect result to 0. | |
0: Normal operation | ||||||
This bit should not be set if 0x05[7] is also set. | ||||||
5 | 0 | RW | Y | EQ_REFA_SEL[1] | Signal detect assert thresholds. Refer to the Programming Guide for more information. | |
4 | 0 | RW | Y | EQ_REFA_SEL[0] | ||
3 | 0 | RW | Y | EQ_REFD_SEL[1] | Signal detect de-assert thresholds. Refer to the Programming Guide for more information. | |
2 | 1 | RW | Y | EQ_REFD_SEL[0] | ||
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x06 | 0xC0 | GPIO2 Config | ||||
7 | 1 | RW | Y | DRV_SEL_VOD[1] | Driver VOD adjust (DC gain). Refer to the Programming Guide for more information. | |
6 | 1 | RW | Y | DRV_SEL_VOD[0] | ||
5 | 0 | RW | Y | DRV_EQ_PD_OV | 1: Driver and equalizer power down manually with Reg_0x06[3] and Reg_0x04[3], respectively. | |
0: Driver and equalizer are powered down or up by default when LOS=1/0. | ||||||
4 | 0 | RW | Y | DRV_SEL_MUTE _OV | Driver mute override: | |
1: Use register 0x06[1] for mute control. | ||||||
0: Normal operation. Mute is automatically controlled by signal detect. | ||||||
3 | 0 | RW | Y | DRV_PD | 1: Power down the driver. | |
0: Normal operation, driver power on or off is controlled by signal detect. | ||||||
2 | 0 | RW | Y | DRV_PD_CM_LOOP | 1: Disable the driver’s common mode loop control circuit. | |
0: Normal operation, common mode loop enabled. | ||||||
1 | 0 | RW | Y | DRV_SEL_MUTE | 1: Mute driver if override bit is enabled. | |
0: Normal operation | ||||||
0 | 0 | RW | Y | DRV_SEL_SOURCE | Select the signal source for the current channel's driver using the cross-point. 1: Transmit the signal from the adjacent channel. | |
0: Transmit the signal from the local channel. | ||||||
0x07 | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | Y | MUX_INV_PIN_CTRL | Invert the mux pin control. Only applicable if Shared Reg_0x05[1]=1. For channels 0, 1, 4, and 5 (controlled by MUXSEL0): 0: If MUXSEL0=0, channel is in straight-thru mode. If MUXSEL0=1, channel output is from adjacent channel's EQ. 1: If MUXSEL0=1, channel is in straight-thru mode. If MUXSEL0=0, channel output is from adjacent channel's EQ. For channels 2, 3, 6, and 7 (controlled by MUXSEL1): 0: If MUXSEL1=0, channel is in straight-thru mode. If MUXSEL1=1, channel output is from adjacent channel's EQ. 1: If MUXSEL1=1, channel is in straight-thru mode. If MUXSEL1=0, channel output is from adjacent channel's EQ. | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x08 | 0x50 | |||||
7 | 0 | RW | Y | RESERVED | RESERVED | |
6 | 1 | RW | Y | RESERVED | RESERVED | |
5 | 0 | RW | Y | RESERVED | RESERVED | |
4 | 1 | RW | Y | RESERVED | RESERVED | |
3 | 0 | RW | Y | BG_SEL_IPTAT25 | 1: Increases the current to the CTLE by 5%. | |
0: Default | ||||||
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x09 | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x0A | 0x30 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | Y | SD_EN_FAST | 1: Fast signal detect enabled. 0: Fast signal detect disabled. | |
5 | 1 | RW | Y | SD_REF_HIGH | Signal detect threshold controls: 11: Normal operation 10: Signal detect assert or de-assert thresholds reduced. 01: Signal detect assert or de-assert thresholds reduced. 00: Signal detect assert or de-assert thresholds reduced. | |
4 | 1 | RW | Y | SD_GAIN | ||
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x0B | 0x1A | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 1 | RW | Y | RESERVED | RESERVED | |
3 | 1 | RW | Y | RESERVED | RESERVED | |
2 | 0 | RW | Y | RESERVED | RESERVED | |
1 | 1 | RW | Y | RESERVED | RESERVED | |
0 | 0 | RW | Y | RESERVED | RESERVED | |
0x0C | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | Y | RESERVED | RESERVED | |
2 | 0 | RW | Y | RESERVED | RESERVED | |
1 | 0 | RW | Y | RESERVED | RESERVED | |
0 | 0 | RW | Y | RESERVED | RESERVED | |
0x0D | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | Y | RESERVED | RESERVED | |
2 | 0 | RW | Y | RESERVED | RESERVED | |
1 | 0 | RW | Y | RESERVED | RESERVED | |
0 | 0 | RW | Y | RESERVED | RESERVED | |
0x0E | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x0F | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | Y | BG_SEL_IPP100[1] | CTLE bias programming. BG_SEL_IPP100[2] is in Reg_0x04[1]. 000: 0% additional current (Default) 001: 5% additional current 010: 10% additional current 011: 15% additional current 100: 20% additional current 101: 25% additional current 110: 30% additional current 111: 35% additional current | |
4 | 0 | RW | Y | BG_SEL_IPP100[0] | ||
3 | 0 | RW | Y | BG_SEL_IPH200 _v1[1] | Program pre-driver bias current: 00: 0% additional current (Default) 01: 12.5% additional current 10: 25% additional current 11: 37.5% additional current | |
2 | 0 | RW | Y | BG_SEL_IPH200 _v1[0] | ||
1 | 0 | RW | Y | BG_SEL_IPH200 _v0[1] | Program driver bias current: 00: 0% additional current (Default) 01: 12.5% additional current 10: 25% additional current 11: 37.5% additional current | |
0 | 0 | RW | Y | BG_SEL_IPH200 _v0[0] | ||
0x10 | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | Y | RESERVED | RESERVED | |
4 | 0 | RW | Y | RESERVED | RESERVED | |
3 | 0 | RW | Y | RESERVED | RESERVED | |
2 | 0 | RW | Y | RESERVED | RESERVED | |
1 | 0 | RW | Y | RESERVED | RESERVED | |
0 | 0 | RW | Y | RESERVED | RESERVED | |
0x11-0x19 | 0x00 | |||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED |