JAJSI38C october 2016 – december 2020 DS280MB810
PRODUCTION DATA
Addr [HEX] | Bit | Default [HEX] | Mode | EEPROM | Field | Description |
---|---|---|---|---|---|---|
0x00 | 0x01 | General | ||||
7 | 0 | R | N | I2C_ADDR[3] | I2C strap observation. The device 7-bit slave address is 0x18 + I2C_ADDR[3:0]. | |
6 | 0 | R | N | I2C_ADDR[2] | ||
5 | 0 | R | N | I2C_ADDR[1] | ||
4 | 0 | R | N | I2C_ADDR[0] | ||
3 | 0 | R | N | RESERVED | RESERVED | |
2 | 0 | R | N | RESERVED | RESERVED | |
1 | 0 | R | N | RESERVED | 1'b when Quad1 Shared registers enabled. | |
0 | 1 | R | N | RESERVED | 1'b when Quad0 Shared registers enabled. | |
0x01 | 0x02 | Version Revision | ||||
7 | 0 | R | N | RESERVED | RESERVED | |
6 | 0 | R | N | RESERVED | RESERVED | |
5 | 0 | R | N | RESERVED | RESERVED | |
4 | 0 | R | N | RESERVED | RESERVED | |
3 | 0 | R | N | RESERVED | RESERVED | |
2 | 0 | R | N | RESERVED | RESERVED | |
1 | 1 | R | N | RESERVED | RESERVED | |
0 | 0 | R | N | RESERVED | RESERVED | |
0x02 | 0x00 | Channel Control | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x03 | 0x00 | Channel Control | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x04 | 0x01 | General | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RWSC | N | RST_I2C_REGS | 1: Reset shared registers, bit is self-clearing. | |
0: Normal operation | ||||||
5 | 0 | RWSC | N | RST_I2C_MAS | 1: Self-clearing reset for I2C master. | |
0: Normal operation | ||||||
4 | 0 | RW | N | FRC_EEPRM_RD | 1: Override EN_SMB and input chain status to force EEPROM Configuration. | |
0: Normal operation | ||||||
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | REGS_CLOCK_EN | RESERVED | |
1 | 0 | RW | N | I2C_MAS_CLK_EN | RESERVED | |
0 | 1 | RW | N | I2CSLV_CLK_EN | RESERVED | |
0x05 | 0x00 | General | ||||
7 | 0 | RW | N | DISAB_EEPRM_CFG | 1: Disable Master Mode EEPROM Configuration (If not started, not effective midway or after configuration). | |
0: Normal operation | ||||||
6 | 0 | RW | N | CRC_EN | RESERVED | |
5 | 0 | RW | N | ML_TEST _CONTROL | RESERVED | |
4 | 0 | R | N | EEPROM_READING _DONE | Sets 1 when EEPROM reading is done. | |
3 | 0 | R | N | RESERVED | RESERVED | |
2 | 0 | R | Y | CAL_CLK_INV_DIS | 1: Disable the inversion of CAL_CLK_OUT. | |
0: Normal operation, CAL_CLK_OUT is inverted with respect to CAL_CLK_IN. | ||||||
1 | 0 | R | N | MUX_CONFIG_PIN_CTRL | 1: MUXSEL0_TEST0 and MUXSEL1_TEST1 are used to configure the cross-point mux. MUXSEL0_TEST0 controls the cross-point for channels 0–1 and 4–5. MUXSEL1_TEST1 controls the cross-point for channels 2–3 and 6–7. For mux pin-control, Reg_05[0] must also be 0, which is the power-on default value. 0: Cross-point mux is configured on a per-channel basis with Reg_0x06[0]. | |
0 | 0 | R | N | TEST0_AS_CAL _CLK | RESERVED | |
0x06 | 0x00 | General | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x07 | 0x00 | General | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | R | N | CAL_CLK_DET | 1: Indicates that CAL_CLK has been detected. | |
0: Indicates that CAL_CLK has not been detected. | ||||||
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | MR_CAL_CLK_DET _DIS | 1: Disable CAL_CLK detect. | |
0: Enable CAL_CLK detect. | ||||||
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | Y | DIS_CAL_CLK_OUT | 1: Disable CAL_CLK_OUT, output is high-Z. | |
0: Enable CAL_CLK_OUT. | ||||||
0x08 | 0x00 | General | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | RW | N | RESERVED | RESERVED | |
0 | 0 | RW | N | RESERVED | RESERVED | |
0x09 | 0x00 | General | ||||
7 | 0 | R | N | RESERVED | RESERVED | |
6 | 0 | R | N | RESERVED | RESERVED | |
5 | 0 | R | N | RESERVED | RESERVED | |
4 | 0 | R | N | RESERVED | RESERVED | |
3 | 0 | R | N | RESERVED | RESERVED | |
2 | 0 | R | N | RESERVED | RESERVED | |
1 | 0 | R | N | RESERVED | RESERVED | |
0 | 0 | R | N | RESERVED | RESERVED | |
0x0A | 0x00 | General | ||||
7 | 0 | RW | N | RESERVED | RESERVED | |
6 | 0 | RW | N | RESERVED | RESERVED | |
5 | 0 | RW | N | RESERVED | RESERVED | |
4 | 0 | RW | N | RESERVED | RESERVED | |
3 | 0 | RW | N | RESERVED | RESERVED | |
2 | 0 | RW | N | RESERVED | RESERVED | |
1 | 0 | R | N | RESERVED | RESERVED | |
0 | 0 | R | N | RESERVED | RESERVED | |
0x0B | 0x00 | |||||
7 | 0 | R | N | EECFG_CMPLT | 11: Not valid. | |
10: EEPROM load completed successfully. | ||||||
6 | 0 | R | N | EECFG_FAIL | 01: EEPROM load failed after 64 attempts. | |
00: EEPROM load in progress. | ||||||
5 | 0 | R | N | EECFG_ATMPT[5] | Indicates number of attempts made to load EEPROM image. | |
4 | 0 | R | N | EECFG_ATMPT[4] | ||
3 | 0 | R | N | EECFG_ATMPT[3] | ||
2 | 0 | R | N | EECFG_ATMPT[2] | ||
1 | 0 | R | N | EECFG_ATMPT[1] | ||
0 | 0 | R | N | EECFG_ATMPT[0] | ||
0x0C | 0x91 | |||||
7 | 1 | RW | N | I2C_FAST | 1: EEPROM load uses Fast I2C Mode (400 kHz). | |
0: EEPROM load uses Standard I2C Mode (100 kHz). | ||||||
6 | 0 | RW | N | I2C_SDA_HOLD[2] | Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SDC input. Units are 100 ns. | |
5 | 0 | RW | N | I2C_ SDA_HOLD[1] | ||
4 | 1 | RW | N | I2C_ SDA_HOLD[0] | ||
3 | 0 | RW | N | I2C_FLTR_DEPTH[3] | I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SDC and SDA inputs that will be rejected. Units are 100 ns. | |
2 | 0 | RW | N | I2C_FLTR_DEPTH[2] | ||
1 | 0 | RW | N | I2C_FLTR_DEPTH[1] | ||
0 | 1 | RW | N | I2C_FLTR_DEPTH[0] |