JAJSOE2 September   2022 DS320PR822

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Receiver Detect State Machine

The DS320PR822 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI express specifications. At power up or after a manual PD0/1 or SEL1/0 toggle the redriver determines whether or not a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR822 provides additional flexibility for system designers to appropriately set the device in desired mode as provided in Table 7-3. PD0 and PD1 pins impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS320PR822 is used for a same PCI express link, then the PD1 and PD0 pins can be shorted and driven together. For most applications the RX_DET pin can be left floating for default settings. In SMBus/I2C mode each channel can be configured independently.

Table 7-3 Receiver Detect State Machine Settings
PD0PD1RX_DETChannels 0-3
Rx Common-mode Impedance		Channels 4-7
Rx Common-mode Impedance		COMMENTS
LLL0Always 50 ΩAlways 50 ΩPCI Express Rx detection state machine is disabled. Recommended for non PCIe interface use case where the DS320PR822 is used as buffer with equalization.
LLL1Pre Detect: Hi-Z
Post Detect: 50 Ω.		Pre Detect: Hi-Z
Post Detect: 50 Ω.		Outputs polls until 3 consecutive valid detections
LLL2Pre Detect: Hi-Z
Post Detect: 50 Ω.		Pre Detect: Hi-Z
Post Detect: 50 Ω.		Outputs polls until 2 consecutive valid detections
LLL3NANAReserved
LLL4 (Float)Pre Detect: Hi-Z
Post Detect: 50 Ω.		Pre Detect: Hi-Z
Post Detect: 50 Ω.		Tx polls every ≅150 µs until valid termination is detected. Rx CM impedance held at Hi-Z until detection Reset by asserting PD0/1 high for 200 µs then low.
HLXHi-ZPre Detect: Hi-Z
Post Detect: 50 Ω.		Reset Channels 0-3 signal path and set their Rx impedance to Hi-Z
LHXPre Detect: Hi-Z
Post Detect: 50 Ω.		Hi-ZReset Channels 4-7 signal path and set their Rx impedance to Hi-Z.
HHXHi-ZHi-Z

In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.