JAJSOE2 September   2022 DS320PR822

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PACT Device active power   8 channels active, EQ = 0-2 1.15 1.42 W
8 channels active, EQ = 5-19 1.41 1.75 W
PRXDET Device power consumption while waiting for far end receiver terminations All channels enabled but no far end receiver detected 166 mW
PSTBY Device power consumption in standby power mode All channels disabled (PD1,0 = H) 23 mW
Control IO
VIH High level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 2.1 V
VIL Low level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.08 V
VOH High level output voltage Rpull-up = 4.7 kΩ (SDA, SCL, ALL_DONE_N pins) 2.1 V
VOL Low level output voltage IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) 0.4 V
IIH,SEL Input high leakage current for SEL pins VInput =  SEL1, SEL0 pins 100 µA
IIH Input high leakage current VInput = VCC, (SCL, SDA, PD1, PD0, READ_EN_N pins) 10 µA
IIL Input low leakage current VInput = 0 V, (SCL, SDA, PD1, PD0, READ_EN_N, SEL1, SEL0 pins) −10 µA
IIH,FS Input high leakage current for fail safe input pins VInput = 3.6 V, VCC = 0 V, (SCL, SDA, , PD1, PD0, READ_EN_N, SEL1, SEL0 pins) 200 µA
CIN-CTRL Input capacitance SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.6 pF
5 Level IOs (MODE, GAIN0, GAIN1, EQ0_0, EQ1_0, EQ0_1, EQ1_1, RX_DET pins)
IIH_5L Input high leakage current, 5-level IOs VIN = 2.5 V 10 µA
IIL_5L Input low leakage current for all 5-level IOs except MODE. VIN = GND −10 µA
IIL_5L,MODE Input low leakage current for MODE pin VIN = GND −200 µA
Receiver
VRX-DC-CM RX DC Common Mode Voltage Device is in active or standby state 1.4 V
ZRX-DC Rx DC Single-Ended Impedance 50 Ω
ZRX-HIGH-IMP-DC-POS DC input CM input impedance during Reset or power-down Inputs are at VRX-DC-CM voltage  15 kΩ
Transmitter
ZTX-DIFF-DC DC Differential Tx Impedance Impedance of Tx during active signaling, VID,diff = 1 Vpp 100 Ω
VTX-DC-CM Tx DC common mode Voltage 1.0 V
ITX-SHORT Tx Short Circuit Current Total current the Tx can supply when shorted to GND 70 mA