SNLS344G July   2011  – August 2015 DS80PCI102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Electrical Characteristics — Serial Management Bus Interface
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 7.5.2 Transfer of Data Through the SMBus
      3. 7.5.3 SMBus Transactions
      4. 7.5.4 Writing a Register
      5. 7.5.5 Reading a Register
      6. 7.5.6 EEPROM Programming
        1. 7.5.6.1 Master EEPROM Programming
        2. 7.5.6.2 EEPROM Address Mapping
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 3.3-V or 2.5-V Supply Mode Operation
    2. 9.2 Power Supply Bypass
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6 Specifications

6.1 Absolute Maximum Ratings (1)(2)

MIN MAX UNIT
Supply voltage (VDD - 2.5 V) –0.5 2.75 V
Supply voltage (VIN - 3.3 V) –0.5 4.0 V
LVCMOS Input/Output Voltage –0.5 4.0 V
CML Input Voltage –0.5 VDD + 0.5 V
CML Input Current –30 30 mA
Junction Temperature 125 °C
Lead temperature soldering (4 s)(3) 260 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute Maximum Numbers are specified for a junction temperature range of –40° C to 125° C. Models are validated to Maximum Operating Voltages only.
(3) For soldering specifications: See application note SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±5000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1250
MM, STD - JESD22-A115-A ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage (2.5-V mode) 2.375 2.5 2.625 V
Supply Voltage (3.3-V mode) 3.0 3.3 3.6 V
Ambient Temperature -40 25 85 °C
SMBus (SDA, SCL) 3.6 V

6.4 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
IDD Supply Current VIN = 3.3-V supply,
EQ = Enabled, RXDET = 1,
VOD = 1.0 Vp-p,
PRSNT = LOW		 50 63 mA
VIN = 3.3-V supply,
PRSNT = HIGH		 9 12 mA
VDD = 2.5 V,
PRSNT = HIGH		 6 9 mA
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25 High-level input voltage
(READ_EN pin)		 2.5-V Mode 2.0 VDD V
VIH33 High-level input voltage
(READ_EN pin)		 3.3-V Mode 2.0 VIN V
VIH High Level Input Voltage
(PRSNT pin)		 2.5-V Mode 0.9 × VDD VDD V
3.3-V Mode 0.9 × VIN VIN
VIL Low Level Input Voltage 0 0.7 V
VOH High Level Output Voltage (DONE pin) IOH = −4 mA 2.0 V
VOL Low Level Output Voltage (DONE pin) IOL = 4 mA 0.4 V
IIH Input High Current (PRSNT pin) VIN Supply = 3.6 V,
Input = 3.6 V		 –15 15 µA
Input High Current with internal resistors
(4–level input pin)		 +20 80 µA
IIL Input Low Current (PRSNT pin) VIN = 3.6 V,
Input = 0 V		 –15 15 µA
Input Low Current with internal resistors
(4–level input pin)		 –160 -40 µA
CML RECEIVER INPUTS (IN_N+, IN_N-)
RLRX-DIFF RX Differential return loss 0.05 to 1.25 GHz –16 dB
1.25 to 2.5 GHz –16 dB
2.5 to 4.0 GHz –14 dB
RLRX-CM RX Common mode return loss 0.05 to 2.5 GHz –12 dB
2.5 to 4.0 GHz –8 dB
ZRX-DC RX DC single-ended impedance VDD = 2.5 V 40 50 60 Ω
ZRX-DIFF-DC RX DC differential mode impedance VDD = 2.5 V 80 100 120 Ω
VRX-DIFF-DC VID - Differential RX peak to peak input voltage 1.2 V
ZRX-HIGH-IMP-DC-POS DC Input common mode impedance for V > 0 VID = 0 to 200 mV,
ENSMB = 0, RXDET = 0,
VDD = 2.5 V		 50 kΩ
VRX-SIGNAL-DET-DIFF-PP Signal detect assert level for active data signal SD_TH = Float,
0101 pattern at 8 Gbps
Measured at pins		 180 mVp-p
VRX-IDLE-DET-DIFF-PP Signal detect deassert level for electrical idle SD_TH = Float,
0101 pattern at 8 Gbps
Measured at pins		 110 mVp-p
HIGH SPEED OUTPUTS
VTX-DIFF-PP Output voltage differential swing Differential measurement with OUT_n+ and OUT_n-,
terminated by 50 Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEMA/B = 0,
VOD_SEL = Float, (1)		 0.8 1.0 1.1 Vp-p
VTX-DE-RATIO_3.5 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEMA/B = Float,
VOD_SEL = Float, (GEN 1, 2 only)		 –3.5 dB
VTX-DE-RATIO_6 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEMA/B = 20 kΩ to GND,
VOD_SEL = Float, (GEN 1, 2 only)		 –6 dB
TTX-RJ Random Ritter VID = 800 mV, 0101 pattern, 8.0 Gbps,
VOD = 1.0 V, EQ = 0x00,
DE = 0 dB		 0.3 ps RMS
TTX-DJ Deterministic Jitter VID = 800 mV,
PRBS15, 8.0 Gbps
VOD = 1.0 V, EQ = 0x00,
DE = 0 dB		 0.05 UIpp
TTX-RISE-FALL TX rise/fall time 20% to 80% of differential output voltage, (3) 34 45 ps
TRF-MISMATCH TX rise/fall mismatch 20% to 80% of differential output voltage, (3) 0.01 UI
RLTX-DIFF TX Differential return loss 0.05 to 1.25 GHz –16 dB
1.25 to 2.5 GHz –12 dB
2.5 to 4 GHz –11 dB
RLTX-CM TX Common mode return loss 0.05 to 2.5 GHz –12 dB
2.5 to 4 GHz –8 dB
ZTX-DIFF-DC DC differential TX impedance 100 Ω
VTX-CM-AC-PP TX AC common mode voltage VOD = 1.0 Vp-p,
DEMA/B = 0,
VOD_SEL = Float, (3)		 100 mVp-p
ITX-SHORT TX short circuit current limit Total current the transmitter can supply when shorted to VDD or GND 20 mA
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute delta of DC common mode voltage during L0 and electrical idle (3)  100 mV
VTX-CM-DC-LINE-DELTA Absolute delta of DC common mode voltgae between TX+ and TX- (3)  25 mV
TTX-IDLE-DATA Max time to transition to differential DATA signal after IDLE VID = 1.0 Vp-p, 8 Gbps 3.5 ns
TTX-DATA-IDLE Max time to transition to IDLE after differential DATA signal VID = 1.0 Vp-p, 8 Gbps 6.5 ns
TPLHD/PHLD High-to-Low and Low-to-High Differential Propagation Delay DE = 0, EQ = 0x00, (2) 200 ps
TLSK Lane-to-lane skew T = 25ºC, VDD = 2.5 V 25 ps
TPPSK Part-to-part propagation delay skew T = 25ºC, VDD = 2.5 V 40 ps
EQUALIZATION
DJE1 Residual deterministic jitter at
8 Gbps		 35” 4mils FR4,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x1F, DEM = 0 dB		 0.14 UIpp
DJE2 Residual deterministic jitter at
5 Gbps		 35” 4mils FR4,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x1F, DEM = 0 dB		 0.1 UIpp
DJE3 Residual deterministic jitter at 2.5 Gbps 35” 4mils FR4,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x1F, DEM = 0 dB		 0.05 UIpp
DJE4 Residual deterministic jitter at
8 Gbps		 10 meters 30-awg cable,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x2F, DEM = 0 dB		 0.16 UIpp
DJE5 Residual deterministic jitter at
5 Gbps		 10 meters 30-awg cable,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x2F, DEM = 0 dB		 0.1 UIpp
DJE6 Residual deterministic jitter at 2.5 Gbps 10 meters 30-awg cable,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x2F, DEM = 0 dB		 0.05 UIpp
DE-EMPHASIS (GEN 1&2 MODE ONLY)
DJD1 Residual deterministic jitter at 2.5 Gbps and 5.0 Gbps 10” 4mils FR4,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x00, VOD = 1.0 Vp-p,
DEM = −3.5 dB		 0.1 UIpp
DJD2 Residual deterministic jitter at 2.5 Gbps and 5.0 Gbps 20” 4mils FR4,
VID = 0.8 Vp-p, PRBS15,
EQ = 0x00, VOD = 1.0 Vp-p,
DEM = −9 dB		 0.1 UIpp
(1) In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS80PCI102 repeater in GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake negotiation link training.
(2) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 0x00 will result in the shortest propagation delays.
(3) Parameter is characterized but not tested in production.

6.5 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL Data, Clock Input Low Voltage 0.8 V
VIH Data, Clock Input High Voltage 2.1 3.6 V
IPULLUP Current Through Pullup Resistor or Current Source High Power Specification 4 mA
VDD Nominal Bus Voltage 2.375 3.6 V
ILEAK-Bus Input Leakage Per Bus Segment (1)  -200 200 µA
ILEAK-Pin Input Leakage Per Device Pin -15 µA
CI Capacitance for SDA and SCL (1)(2) 10 pF
RTERM External Termination Resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% Pullup VDD = 3.3 V(1)(2)(3) 2000 Ω
Pullup VDD = 2.5 V(1)(2)(3) 1000 Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB Bus Operating Frequency ENSMB = VDD (Slave Mode) 400 kHz
ENSMB = FLOAT (Master Mode) 280 400 520 kHz
TBUF Bus Free Time Between Stop and Start Condition 1.3 µs
THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. At IPULLUP, Max 0.6 µs
TSU:STA Repeated Start Condition Setup Time 0.6 µs
TSU:STO Stop Condition Setup Time 0.6 µs
THD:DAT Data Hold Time 0 ns
TSU:DAT Data Setup Time 100 ns
TLOW Clock Low Period 1.3 µs
THIGH Clock High Period (4)  0.6 50 µs
tF Clock/Data Fall Time (4)  300 ns
tR Clock/Data Rise Time (4)  300 ns
tPOR Time in which a device must be operational after power-on reset (4)(5)  500 ms
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.
(5) Specified by Design. Parameter not tested in production.

6.6 Timing Diagrams

DS80PCI102 edge.gifFigure 1. CML Output and Rise and Fall Times
DS80PCI102 30156903.gifFigure 2. Propagation Delay Timing Diagram
DS80PCI102 30156904.gifFigure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
DS80PCI102 30156901.gifFigure 4. SMBus Timing Parameters

6.7 Typical Characteristics

DS80PCI102 30133328.gifFigure 5. Output Differential Voltage (VOD = 1.0 Vp-p) vs Supply Voltage (VDD)
DS80PCI102 30133329.gifFigure 6. Output Differential Voltage (VOD = 1.0 Vp-p) vs Temperature