JAJSFF6B june   2018  – september 2020 DS90C189-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Typical Application Diagrams
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
    1.     DS90C189 Pin Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 AEC-Q100 Qualified
      2. 8.3.2 ESD Protection
      3. 8.3.3 Operating Modes
      4. 8.3.4 LVDS Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Single Pixel Input / Single Pixel Output
      3. 8.4.3 Single Pixel Input / Dual Pixel Output
      4. 8.4.4 Pixel Clock Edge Select (RFB)
      5. 8.4.5 Power Management
      6. 8.4.6 Sleep Mode (PDB)
      7. 8.4.7 LVDS Outputs
      8. 8.4.8 LVCMOS Inputs
    5. 8.5 Programming
      1. 8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.5.1.1 Color Mapping Information
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 AC Timing Diagrams

GUID-2F2E5ED8-B852-4D9D-9D90-B10F4E41093E-low.gif
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. Figure 7-2 shows a falling edge data strobe (IN_CLK).
Figure 7-1 Checker Board Test Pattern
GUID-506C4CB5-A182-4D76-BE48-603C8262CF3D-low.gif
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C. Figure 7-2 shows a falling edge data strobe (IN_CLK).
Figure 7-2 “16 Gray Scale” Test Pattern (Falling Edge Clock shown)
GUID-E396DCA8-FA9A-429B-B1BE-CFE173736501-low.gifFigure 7-3 DS90C189-Q1 (Transmitter) LVDS Output Load
GUID-4AE8099F-6AD5-48C7-B0BA-4C286C20F27E-low.gifFigure 7-4 LVDS Output Transition Times
GUID-9A473077-926F-4CCF-84CF-5DCA5ADA7993-low.gifFigure 7-5 LVCMOS Input Transition Times
GUID-40D4411D-B28B-47C6-85C9-68597E4523F3-low.gifFigure 7-6 LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
GUID-48760667-F139-4608-ADB0-52B7F9BD6B3A-low.gifFigure 7-7 Start Up / Phase Lock Loop Set Time
GUID-1E9025EF-3B9E-461A-9E85-A977BC8D5359-low.gifFigure 7-8 Sleep Mode / Power Down Delay
GUID-0F5B9E19-9721-495E-BD53-D109647716AC-low.gifFigure 7-9 LVDS Serial Bit Positions
GUID-694D98F3-846B-4A66-8E34-E9DB2819CFC3-low.gifFigure 7-10 Single In, Dual Out Mode Timing and Latency
GUID-B5E0373E-A49B-48D8-A9AA-CCAC55FCDA35-low.gifFigure 7-11 Single In, Single Out Mode Timing and Latency